KR-102964113-B1 - System and Method for Pivot-Based Load-Balanced Memory Repair

Abstract

The present invention relates to a pivot-based equal load memory repair system and method, comprising: a pivot analysis unit that analyzes memory failure information collected during testing and calculates the number of pivot failures included in each memory; a sorting unit that sorts each memory in descending order based on the number of pivot failures calculated by the pivot analysis unit; a memory mapping unit that sequentially distributes the memories sorted by the sorting unit to a plurality of repair core groups in a round-robin manner; and a repair execution unit composed of a plurality of repair cores that sequentially perform repair operations on the memories allocated from the memory mapping unit.

Inventors

• 강성호
• 정유진
• 정재영

Assignees

• 연세대학교 산학협력단

Dates

Publication Date

20260512

Application Date

20250808

Claims (20)

1. A pivot analysis unit (110) that analyzes memory failure information collected during testing and calculates the number of pivot failures included in each memory; A sorting unit (120) that sorts each memory in descending order based on the number of pivot failures calculated by the pivot analysis unit (110); A memory mapping unit (130) that sequentially distributes the memories aligned by the alignment unit (120) to a plurality of repair core groups in a round-robin manner; and A repair execution unit (140) comprising a plurality of repair cores that sequentially perform repair operations on memory allocated from the memory mapping unit (130), Pivot-based equal load memory repair system.
2. In paragraph 1, The above pivot analysis unit (110) is, Registering identification information of failure items located in the same row or same column among the failure items included in each memory in a separation table, and setting the number of failure items not registered in the table as the pivot failure count. Pivot-based equal load memory repair system.
3. In paragraph 1, The above pivot analysis unit (110) is, A method of storing the number of pivot failures by creating a fixed-size array based on the total number of memory units, and whenever failure information is collected, referencing the index of the array corresponding to the memory unit and cumulatively updating the value of the corresponding position in the array. Pivot-based equal load memory repair system.
4. In paragraph 1, The above pivot analysis unit (110) is, It operates as an execution thread independent of the test controller whenever fault information is received, and if the row address and column address of the fault information are not included in the registered fault table, it classifies the fault as a pivot item and updates the pivot count storage array in real time. Pivot-based equal load memory repair system.
5. In paragraph 1, The above pivot analysis unit (110) is, Storing the row and column addresses of each fault in a fault table, and if new fault information is not included in any row or column of the table, determining the fault as a pivot and increasing the pivot count value corresponding to the memory base. Pivot-based equal load memory repair system.
6. In paragraph 1, The above alignment unit (120) is, Comparing the items in the pivot failure count array to sort in descending order of pivot failure count, and if the pivot failure counts are the same, determining the sorting order in descending order of memory radix, Pivot-based equal load memory repair system.
7. In paragraph 1, The above memory mapping unit (130) is, Iterating through a sorted memory array in order and distributing each memory to multiple repair cores in a sequential rotational manner according to the order of iteration, Pivot-based equal load memory repair system.
8. In paragraph 1, The above memory mapping unit (130) is, Calculating the total number of pivot failures of memory bundles distributed to each repair core, and if the difference between the totals is greater than or equal to a preset threshold, readjusting the memory insertion order to perform iterative distribution, Pivot-based equal load memory repair system.
9. In paragraph 1, The above memory mapping unit (130) is, After a termination signal indicating that the collection of fault information for the entire memory is complete is input, sorting and repair core distribution based on the number of pivot faults is performed. Pivot-based equal load memory repair system.
10. In paragraph 1, The above repair performing unit (140) is, Referencing a fault address table for the repair target for the memory allocated to each repair core, executing a repair algorithm branched according to the fault location and type on a thread-by-thread basis, and performing the branch execution in parallel. Pivot-based equal load memory repair system.
11. A step of calculating the number of pivot failures contained in each memory by analyzing failure information collected during testing through a pivot analysis unit; A step of sorting each memory in descending order based on the number of pivot failures through a sorting unit; A step of sequentially distributing aligned memory to a plurality of repair core groups in a round-robin manner through a memory mapping unit; and A method comprising the step of performing repair operations sequentially on each distributed memory through a repair execution unit, Pivot-based even load memory repair method.
12. In Paragraph 11, The step of calculating the number of pivot failures mentioned above is, A step of storing identification information of fault items located in the same row or same column among the fault items contained in each memory in a fault registration table; and The method includes the step of counting the number of failure items not registered in the table above and setting the number as the pivot failure count. Pivot-based even load memory repair method.
13. In Paragraph 11, The step of calculating the number of pivot failures mentioned above is, A step of generating a fixed-size array to identify the entire memory; and The method includes the step of accumulating and storing the number of pivot failures by referencing an array index corresponding to the base of the memory where the failure occurred whenever failure information is collected, and increasing the value at the index position by 1. Pivot-based even load memory repair method.
14. In Paragraph 11, The step of calculating the number of pivot failures mentioned above is, A step of performing pivot analysis in an execution thread separated from the test controller whenever fault information is received; A step of comparing the row address and column address of the received fault information with a fault registration table; and If the above address is not included in the fault registration table, the method includes the step of determining the corresponding fault as a pivot and updating the value of the pivot count storage array corresponding to the memory identification index. Pivot-based even load memory repair method.
15. In Paragraph 11, The step of calculating the number of pivot failures mentioned above is, The step of storing the row address and column address of each fault in a fault registration table; and Subsequently, if the row address and column address of the received fault information are not included in any item of the table, the step of determining the fault as a pivot and increasing the pivot count value corresponding to the identification index of the memory is included. Pivot-based even load memory repair method.
16. In Paragraph 11, The step of sorting each of the above memories in descending order is, A step of comparing the number of pivot failures corresponding to each memory and sorting the memories in order from largest to smallest number of pivot failures; and For memories with the same number of pivot failures, the method includes the step of determining the sorting order in order of lowest memory base. Pivot-based even load memory repair method.
17. In Paragraph 11, The step of sequentially distributing using the above round-robin method is, Step of sequentially iterating through an aligned memory array; and The method includes the step of distributing each circulated memory to a plurality of repair cores in a sequential rotational manner according to the number of repair cores. Pivot-based even load memory repair method.
18. In Paragraph 11, The step of sequentially distributing using the above round-robin method is, A step of calculating the total number of pivot failures of memory bundles distributed to each repair core; A step of determining whether the difference in the total sum of pivot failures between repair cores is greater than or equal to a preset threshold; and If the above threshold is exceeded, the method includes the step of reallocating memory by readjusting the insertion order of the sorted memory array. Pivot-based even load memory repair method.
19. In Paragraph 11, The step of sequentially distributing using the above round-robin method is, A step of determining whether a termination signal indicating that the collection of fault information for the entire memory has been completed has been received; and After the above termination signal is received, the method includes the step of aligning the memory based on the number of pivot failures and distributing it to a plurality of repair cores. Pivot-based even load memory repair method.
20. In Paragraph 11, The step of performing the above repair operation is, A step of referring to a fault address table corresponding to the memory allocated to each repair core; A step of determining the execution path of a repair algorithm based on the fault location and fault type included in the above table; and The step of executing a repair algorithm for each memory in parallel threads according to a determined execution path, Pivot-based even load memory repair method.

Description

System and Method for Pivot-Based Load-Balanced Memory Repair The present invention relates to a pivot-based equal load memory repair system and method, and more specifically, to a pivot-based equal load memory repair system and method configured to quantitatively distribute the processing load required for fault repair and improve overall repair efficiency by analyzing the number of pivot failures of each memory block based on failure information generated during a memory test process, and performing parallel repairs by evenly distributing the aligned memory to a plurality of repair cores according to the result. Recently, the density and complexity of physical failures occurring in high-density semiconductor memory devices have been increasing, and accordingly, the importance of memory repair technology for repairing or bypassing defective data is being emphasized. In particular, in 3D stacked semiconductor structures, failure patterns between memory cells in each layer appear diverse and non-linear, and if multiple repair resources (e.g., redundant rows/columns, spare blocks, etc.) are not efficiently allocated, the overall chip yield can rapidly decrease. Against this backdrop, if balanced distribution based on failure characteristics or repair difficulty is not considered when distributing memory to repair cores or repair units, a load imbalance problem occurs in which the repair load is concentrated on some repair cores, leading to increased repair time and inefficiency of parallel repair resources. Conventional memory repair systems have mostly relied on methods such as distributing memory to be repaired based on simple address order or test scan order, or statically allocating resources based on their physical locations. In these cases, the absence of quantitative distribution criteria based on the number of failures or repair complexity among memories frequently leads to bottlenecks where the total repair time is limited by the maximum load between repair cores. Furthermore, existing techniques for analyzing memory failures are limited to simple failure count aggregation or evaluations based on the total bit error rate, and lack methods that consider the complexity of actual repair algorithms or structural repairability (e.g., matrix collision avoidance). Accordingly, there is a need for technology that can predict the repair burden based on the spatial distribution and repairability of memory failures, and distribute memory evenly to repair cores based on those criteria. FIG. 1 is a schematic diagram illustrating a memory repair tree structure including one pivot failure according to the prior art and an example of the corresponding search path. FIG. 2 is a schematic diagram illustrating a multi-memory repair tree structure including three pivot failures according to the prior art and an example of a search path therefor. FIG. 3 is a schematic diagram showing the overall configuration of a pivot-based equal load memory repair system (100) according to one embodiment of the present invention. FIG. 4 is a block diagram schematically illustrating the operation flow of a pivot-based equal load memory repair system (100) according to an embodiment of the present invention. FIG. 5 is a block diagram schematically illustrating the pivot fault determination and pivot count update process in a preprocessor according to an embodiment of the present invention. FIG. 6 is a schematic diagram illustrating the process of aligning memory based on the number of pivot failures according to an embodiment of the present invention and distributing it to a plurality of repair cores in a round-robin manner. FIG. 7 is a flowchart illustrating a pivot fault detection and pivot count update procedure according to an embodiment of the present invention. FIG. 8 is a flowchart illustrating a memory alignment and repair core distribution procedure based on the number of pivot failures according to an embodiment of the present invention. FIG. 9 is a flowchart illustrating a parallel repair process for each repair core according to an embodiment of the present invention. FIG. 10 is a flowchart illustrating the entire process of a pivot-based equal load memory repair method according to one embodiment of the present invention in a series of sequences. The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. The terms used in this specification will be briefly explained, and the invention will be described in deta