KR-102964114-B1 - Method and apparatus for Memory Repair Analysis Using Shared Spare Cells

KR102964114B1KR 102964114 B1KR102964114 B1KR 102964114B1KR-102964114-B1

Abstract

A memory repair analysis method based on a shared reserve cell according to the present invention comprises: receiving address information of a fault cell; storing the received address information of the fault cell in a content-based search memory separated to correspond to a local reserve cell and a shared reserve cell, respectively; determining a repair direction for each memory block based on the stored fault information and searching for a reserve cell repair combination including at least one of a local reserve cell and a shared reserve cell based on the repair direction; and verifying whether the repair combination is valid by considering the physical arrangement structure of the shared reserve cell and the number of shared reserve cells that can be allocated per memory block for the searched repair combination.

Inventors

강성호
손누리
이상준

Assignees

연세대학교 산학협력단

Dates

Publication Date: 20260512
Application Date: 20250812

Claims (20)

In memory repair analysis methods, Step of receiving address information of a faulty cell; A step of storing address information of a received fault cell in a content-based search memory separated to correspond to a local reserve cell and a shared reserve cell, respectively; Based on stored fault information, determining a repair direction for each memory block, and based on the repair direction, searching for a spare cell repair combination including at least one of a local spare cell and a shared spare cell; and A step of verifying whether a found repair combination is valid by considering the physical arrangement structure of shared reserve cells and the number of shared reserve cells that can be allocated per memory block; Shared reserve cell-based memory repair analysis method.
In paragraph 1, Before storing the address information of the above fault cell, The step of classifying the address information of the fault cell into pivot faults and non-pivot faults; further comprising Shared reserve cell-based memory repair analysis method.
In paragraph 2, the step of searching for the preliminary cell repair combination is, A step of determining the repair direction based on the above pivot failure; comprising Shared reserve cell-based memory repair analysis method.
In paragraph 2, the step of searching for the preliminary cell repair combination is, Regarding non-pivot failures, a step of identifying pivot failures associated with said non-pivot failures; and A step of searching for a repair combination by considering the corresponding first pivot fault and the associated first non-pivot fault together; comprising Shared reserve cell-based memory repair analysis method.
In claim 1, the step of storing the address information of the fault cell is, A step of determining to terminate the repair analysis process early when the storage space of the above-mentioned content-based search memory is insufficient; comprising Shared reserve cell-based memory repair analysis method.
In paragraph 2, the step of determining the repair direction based on the pivot failure is, A step of determining whether the repair directions between intersecting pivot fault lines conflict; and A step of excluding the corresponding repair combination from the search target when the above collision condition is satisfied; comprising Shared reserve cell-based memory repair analysis method.
In paragraph 1, the step of searching for the above-mentioned repair combination is, A step comprising: applying a condition restricting the inclusion of shared reserve cells in the repair combination only when local reserve cells do not exist or are insufficient to be repairable; Shared reserve cell-based memory repair analysis method.
In paragraph 1, the content-based search memory is, A first content-based search memory that stores fault information corresponding to a local spare cell, and A second content-based search memory configured to store fault information corresponding to a shared spare cell, Shared reserve cell-based memory repair analysis method.
In paragraph 1, The step of determining that repair is impossible and terminating the repair analysis if the above repair combination does not satisfy the arrangement structure or the number of allocatable shared reserve cells; further comprising Shared reserve cell-based memory repair analysis method.
In paragraph 1, the step of searching for the above-mentioned repair combination is, A filtering step that excludes from the search target repair combinations that exceed the allocatable number of shared reserve cells per memory block Shared reserve cell-based memory repair analysis method.
In a shared reserve cell-based memory repair analysis device, A fault information collection unit that receives address information of a fault cell and stores the received fault information in a content-based search memory corresponding to a local spare cell and a shared spare cell; A reserve cell combination analysis unit that determines the repair direction of each memory block based on the above-mentioned stored fault information and searches for a reserve cell repair combination including at least one of a local reserve cell and a shared reserve cell; A repair control signal generation unit that generates a repair control signal for the above-mentioned searched repair combinations and determines a repairable combination by checking for duplication of repair solutions; and A shared reserve cell validation unit that verifies whether the above repair combination satisfies the physical arrangement structure of the shared reserve cell and the number of shared reserve cells that can be allocated per memory block; comprising Shared spare cell-based memory repair analysis device.
In claim 11, the fault information collection unit, After classifying the address information of fault cells into pivoted faults and non-pivoted faults, storing it in the respective content-based search memory corresponding to local spare cells and shared spare cells, Shared spare cell-based memory repair analysis device.
In claim 12, the preliminary cell combination analysis unit is, Determining the repair direction based on pivot failure Shared spare cell-based memory repair analysis device.
In claim 12, the preliminary cell combination analysis unit is, Identifying associated pivot faults for non-pivot faults, and exploring repair combinations by considering the non-pivot faults associated with the said pivot faults together, Shared spare cell-based memory repair analysis device.
In claim 11, the fault information collection unit, Includes a condition determination function that terminates the repair analysis process early when storage space for content-based search memory is insufficient, Shared spare cell-based memory repair analysis device.
In claim 12, the preliminary cell combination analysis unit is, Determining whether repair directions between intersecting pivot fault lines conflict, and excluding the corresponding repair combination from the search target if the conflict condition is satisfied, Shared spare cell-based memory repair analysis device.
In claim 11, the preliminary cell combination analysis unit, Restricting the inclusion of shared reserve cells in the repair combination only when local reserve cells do not exist or are insufficient to be repairable, Shared spare cell-based memory repair analysis device.
In claim 11, the fault information collection unit, A first content-based search memory that stores fault information corresponding to a local spare cell, and A second content-based search memory configured separately to store fault information corresponding to a shared spare cell, Shared spare cell-based memory repair analysis device.
In claim 11, the shared preliminary cell validity verification unit, If a repair combination does not satisfy the physical layout structure or the number of allocatable shared reserve cells, determine the repair combination as unrepairable and terminate the analysis, or filter out combinations that exceed the number of allocatable shared reserve cells per memory block. Shared spare cell-based memory repair analysis device.
In a storage medium storing computer-readable instructions, When the above instructions are executed by a computing device, the computing device, Operation of receiving address information of a faulty cell; An operation of storing address information of a received fault cell in a content-based search memory separated to correspond to a local spare cell and a shared spare cell, respectively; The operation of determining a repair direction for each memory block based on stored fault information, and searching for a spare cell repair combination including at least one of a local spare cell and a shared spare cell based on the repair direction; and For a searched repair combination, performing an operation to verify whether the repair combination is valid by considering the physical arrangement structure of the shared reserve cells and the number of shared reserve cells that can be allocated per memory block; Storage medium.

Description

Method and apparatus for Memory Repair Analysis Using Shared Spare Cells The present invention relates to a repair technology for improving the yield of a highly integrated semiconductor memory device, and more specifically, to a shared spare cell-based memory repair analysis device and method that enables effective repair of a faulty cell by considering a combination of a local spare cell and a shared spare cell. In addition, the present invention relates to a technology for enhancing the performance of a Built-In Redundancy Analysis (BIRA) system by utilizing Content Addressable Memory (CAM) based on fault cell address information within memory to store fault information, and by analyzing valid repair combinations based on the relationship between pivot faults and non-pivot faults, the conditions for allocating shared reserve cells, and the physical arrangement structure. In the manufacturing process of semiconductor memory devices, the occurrence of failed cells due to microfabrication is inevitable, and repair technology to replace failed cells with spare cells is essential to improve product yield. Built-In Redundancy Analysis (BIRA) is widely used as a representative method to support such repair technology, and BIRA enables normal operation by diagnosing faulty cells in memory and allocating redundancy cells. In the conventional BIRA method, the structure is generally based on local spare cells existing in the same memory block as the faulty cell, and the repair algorithm forms a repair combination by utilizing only the spare cells within that block. However, if the distribution of faulty cells is non-uniform or a large number of failures are concentrated in a specific area, there is a limitation in that it is difficult to form a repairable combination using only local spare cells. To address this, research is being conducted on introducing common spare cells that can be shared between adjacent blocks; however, since common spare cells are structured to be accessed by multiple blocks simultaneously, conditions such as redundant allocation, physical placement constraints, and limitations on the number of allocatable cells must be considered at the same time. Consequently, there is a problem in that the algorithm for determining the validity of mathematical combinations becomes very complex and the amount of computation increases significantly. Furthermore, a simple repair method that does not consider the influence relationships between faulty cells can lead to unnecessary or redundant allocation of spare cells, which results in a decrease in overall repair efficiency. Therefore, a sophisticated repair analysis device and method are required that encompass pivot failure-based repair direction determination, duplicate repair elimination, and validation, while also considering the placement conditions and quantity limitations of shared spare cells. FIGS. 1a and 1b are drawings illustrating the structure of a memory block and a spare cell to which a shared spare cell-based memory repair analysis device according to one embodiment of the present invention can be applied. FIG. 2 is a block diagram of a shared reserve cell-based memory repair analysis device (100) according to one embodiment of the present invention. FIGS. 3a and 3b are exemplary configuration diagrams showing various Content Addressable Memory (CAM) structures used in a shared reserve cell-based memory repair analysis device according to an embodiment of the present invention. FIG. 4 is a flowchart illustrating a fault information collection procedure according to one embodiment of the present invention. FIG. 5 is a drawing for explaining an example of fault information storage and reserve cell allocation according to an embodiment of the present invention, where FIG. 5a shows an example in which a fault occurs in a plurality of memory blocks, and FIG. 5b shows an example of each content-based search memory (CAM) in which fault information is stored in correspondence. FIG. 6 shows a flowchart of the repair analysis process of a shared reserve cell-based memory repair analysis device according to one embodiment of the present invention. FIG. 7 is a diagram illustrating an example of the operation of a redundancy analyzer according to an embodiment of the present invention. FIG. 8 shows an example of a shared reserve cell checker circuit structure for the case where a total of four memory blocks exist in one embodiment of the present invention. FIGS. 9a and 9b are drawings illustrating the structure and operation examples of a Common Spare Allocation Logic according to an embodiment of the present invention. The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These