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KR-102964235-B1 - METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

KR102964235B1KR 102964235 B1KR102964235 B1KR 102964235B1KR-102964235-B1

Abstract

A method for manufacturing a semiconductor device according to an embodiment of the present invention comprises the steps of: forming a stacked structure by alternately stacking interlayer insulating layers and sacrificial layers on an upper surface of a substrate; forming first openings spaced apart from each other in a first direction by partially removing the stacked structure from the upper surface so as to penetrate at least one sacrificial layer among the sacrificial layers; forming a first filling insulating layer that fills the first openings; forming a second opening by partially removing the stacked structure from the upper surface so as to penetrate the at least one sacrificial layer between the first openings along the first direction; removing the at least one sacrificial layer exposed through the second opening; and forming a second filling insulating layer in the area where the at least one sacrificial layer was removed and in the second opening, wherein the at least one sacrificial layer is entirely removed between the first openings along the first direction.

Inventors

  • 최현묵
  • 김지홍
  • 나경조

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260513
Application Date
20211206

Claims (10)

  1. A step of preparing a first semiconductor structure by forming circuit elements on a first substrate; A step of forming a second substrate forming a second semiconductor structure on the first semiconductor structure; A step of forming a first stacked region of a stacked structure by alternately stacking first interlayer insulating layers and a first sacrificial layer extending along a first direction on the upper surface of the second substrate; A step of forming a second stacked region of the stacked structure by alternately stacking second interlayer insulating layers and second sacrificial layers extending along the first direction on the first stacked region; A step of partially removing the second stacked region to form first openings that penetrate the second sacrificial layers and are spaced apart from each other in the first direction; A step of forming a first filling insulating layer that fills the first openings; A step of forming a second opening penetrating the second sacrificial layers by partially removing the second stacked region between the first openings along the first direction; A step of removing the second sacrificial layers exposed through the second opening; A step of forming a lower separation region comprising the first and second charging insulating layers by forming regions from which the second sacrificial layers have been removed and a second charging insulating layer filling the second opening; A step of forming a third stacked region of the stacked structure by alternately stacking third interlayer insulating layers extending along the first direction and third sacrificial layers on the first and second charged insulating layers; A step of forming channel structures penetrating the above-mentioned stacked structure; A step of forming third openings that penetrate the laminated structure and extend in the first direction, exposing a portion of the first and second filling insulation layers of the lower separation region; A step of removing the first to third sacrificial layers exposed through the third openings; and A method for manufacturing a semiconductor device comprising the step of forming first to third gate electrodes by filling each of the regions from which the first to third sacrificial layers have been removed with a conductive material.
  2. In Article 1, A method for manufacturing a semiconductor device, wherein in the step of removing the second sacrificial layers exposed through the second opening, the second sacrificial layers are removed to form tunnel portions, and the first filling insulating layer is exposed through the tunnel portions.
  3. In Article 1, A method for manufacturing a semiconductor device in which the above-mentioned third openings are spaced apart from each other along the first direction with the above-mentioned lower separation region in between.
  4. In Article 1, A method for manufacturing a semiconductor device in which the second charge insulating layer is formed by a deposition method different from that of the first charge insulating layer.
  5. In Article 1, A method for manufacturing a semiconductor device in which the width along the first direction of the lower separation region is in the range of 500 nm to 2000 nm.
  6. In Article 1, A method for manufacturing a semiconductor device in which at least some of the second gate electrodes form a ground selection transistor.
  7. In Article 6, A method for manufacturing a semiconductor device in which at least some of the first gate electrodes form an erasure control transistor.
  8. A step of forming a lower stacking region of a stacked structure by alternately stacking lower interlayer insulating layers and lower sacrificial layers extending along a first direction on the upper surface of a substrate; A step of partially removing the lower stacked region to form first openings that penetrate the first lower sacrificial layer among the lower sacrificial layers and are spaced apart from each other in the first direction; A step of forming a first filling insulating layer that fills the first openings; A step of forming a second opening penetrating the first lower sacrificial layer among the lower sacrificial layers by partially removing the lower stacking region between the first openings along the first direction; A step of removing the lower sacrificial layers exposed through the second opening; A step of forming a second filling insulating layer that fills the area where the lower sacrificial layers are removed and the second opening; A step of forming an upper stacking region of the stacked structure by alternately stacking upper interlayer insulating layers and upper sacrificial layers extending along the first direction on the first and second charged insulating layers; A step of forming third openings that penetrate the laminated structure and extend in the first direction, penetrating a portion of the first and second filling insulation layers; The step of removing the lower and upper sacrificial layers through the third opening; and The method includes the step of forming gate electrodes by filling the regions from which the lower and upper sacrificial layers have been removed with a conductive material. A method for manufacturing a semiconductor device in which the third openings are spaced apart from each other along the first direction, and the first and second filling insulating layers remain between the third openings.
  9. In Article 8, A method for manufacturing a semiconductor device in which the first length in the first direction of each of the first openings is greater than the second length in the first direction of the second opening.
  10. A step of forming a stacked structure by alternately stacking interlayer insulating layers and sacrificial layers on the upper surface of a substrate; A step of partially removing the stacked structure from the upper surface to penetrate at least one of the sacrificial layers, thereby forming first openings spaced apart from each other in a first direction; A step of forming a first filling insulating layer that fills the first openings; A step of forming a second opening by partially removing the laminated structure from the upper surface to penetrate the at least one sacrificial layer between the first openings along the first direction; A step of removing the at least one sacrificial layer exposed through the second opening; and The method includes the step of forming a second filling insulating layer in the region where the above-mentioned at least one sacrificial layer has been removed and in the above-mentioned second opening, A method for manufacturing a semiconductor device in which at least one sacrificial layer is entirely removed between the first openings along the first direction.

Description

Method for manufacturing a semiconductor device The present invention relates to a method for manufacturing a semiconductor device. In data storage systems that require data storage, there is a demand for semiconductor devices capable of storing high-capacity data. Accordingly, methods to increase the data storage capacity of semiconductor devices are being studied. For example, as one method to increase the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged in three dimensions instead of memory cells arranged in two dimensions is being proposed. FIG. 1 is a schematic plan view of a semiconductor device according to exemplary embodiments. FIGS. 2a to 2d are schematic cross-sectional views of a semiconductor device according to exemplary embodiments. FIGS. 3a and 3b are partial enlarged views illustrating enlarged portions of a semiconductor device according to exemplary embodiments. FIG. 4 is an exploded perspective view illustrating gate electrodes of a semiconductor device according to exemplary embodiments. FIGS. 5a to 5c are schematic partial enlarged views of a semiconductor device according to exemplary embodiments. FIG. 6 is a schematic cross-sectional view of a semiconductor device according to exemplary embodiments. FIGS. 7a to 17b are schematic cross-sectional views and partial enlarged plan views for illustrating a method of manufacturing a semiconductor device according to exemplary embodiments. FIG. 18 is a schematic diagram illustrating a data storage system including a semiconductor device according to exemplary embodiments. FIG. 19 is a schematic perspective view of a data storage system including a semiconductor device according to an exemplary embodiment. FIG. 20 is a cross-sectional view schematically showing a semiconductor package according to an exemplary embodiment. Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings. FIG. 1 is a schematic plan view of a semiconductor device according to exemplary embodiments. FIGS. 2a through 2d are schematic cross-sectional views of semiconductor devices according to exemplary embodiments. FIGS. 2a through 2d each illustrate cross-sections along the cutting lines I-I', II-II', III-III', and IV-IV' of FIG. 1. FIGS. 3a and 3b are partial enlarged views illustrating some regions of a semiconductor device according to exemplary embodiments. FIG. 3 illustrates the region 'A' of FIG. 2b and the region 'B' of FIG. 2d in enlarged view. Referring to FIGS. 1 through 3b, the semiconductor device (100) may include a peripheral circuit region (PERI), which is a first semiconductor structure including a first substrate (201), and a cell region (CELL), which is a second semiconductor structure including a second substrate (101). The memory cell region (CELL) may be placed on the peripheral circuit region (PERI). In exemplary embodiments, conversely, the cell region (CELL) may be placed below the peripheral circuit region (PERI). The peripheral circuit region (PERI) may include a first substrate (201), source/drain regions (205) and device isolation layers (210) within the first substrate (201), circuit elements (220) disposed on the first substrate (201), circuit contact plugs (270), circuit wiring lines (280), and a peripheral region insulating layer (290). The first substrate (201) may have an upper surface extending in the x and y directions. An active region may be defined in the first substrate (201) by device isolation layers (210). Source/drain regions (205) containing impurities may be disposed in a portion of the active region. The first substrate (201) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first substrate (201) may be provided as a bulk wafer or an epitaxial layer. The circuit elements (220) may include planar transistors. Each circuit element (220) may include a circuit gate dielectric layer (222), a spacer layer (224), and a circuit gate electrode (225). Source/drain regions (205) may be disposed within the first substrate (201) on both sides of the circuit gate electrode (225). Circuit contact plugs (270) and circuit wiring lines (280) may form a circuit wiring structure electrically connected to circuit elements (220) and source/drain regions (205). The circuit contact plugs (270) may have a cylindrical shape, and the circuit wiring lines (280) may have a line shape. The circuit contact plugs (270) and circuit wiring lines (280) may include a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), etc., and each component may further include a diffusion barrier layer. However, in exemplary embodiments, the number of layers and arrangement of the circuit contact plugs (270) and circuit wiring lines (280) may be varied. The peripheral region insulating layer (290) may be disposed to cover th