KR-102964297-B1 - Test Pad and Chip On Film Package Including the same

KR102964297B1KR 102964297 B1KR102964297 B1KR 102964297B1KR-102964297-B1

Abstract

A test pad according to one embodiment of the present invention comprises: a base film divided into a first region and a second region; and a conductive layer located on the first region; wherein the second region is surrounded by the first region on a plane.

Inventors

진승훈
최영민

Assignees

주식회사 엘엑스세미콘

Dates

Publication Date: 20260513
Application Date: 20210712

Claims (15)

A base film divided into a first region and a second region; and A conductive layer located on the first region; comprising The entire outer surface of the second region is surrounded by the first region on a plane, and A test pad characterized in that the second region includes a polygonal shape extended along the second direction.
In Article 1, A test pad characterized in that the conductive layer comprises a first conductive layer located in the first region and a second conductive layer in contact with the first conductive layer on the first conductive layer.
In paragraph 1, A test pad characterized in that the base film is exposed in the second area.
In paragraph 1, A test pad characterized in that a groove is formed in the second region, the side is defined by a conductive layer located in the first region, and the bottom is defined by the base film.
In paragraph 1, It further includes an insulating member located on the conductive layer in the first region, and A test pad characterized in that the conductive layer is located in the first region and the second region.
In paragraph 5, A test pad characterized by having a groove formed in the second region, wherein the side is defined by the insulating member and the bottom is defined by the conductive layer located in the second region.
In paragraph 1, A test pad characterized in that the second region has a width of 20㎛ or more.
In a chip-on-film (COF) package equipped with a predetermined driving integrated circuit, A wiring structure connected to the above-mentioned driving integrated circuit; and A test pad connected to the above wiring structure; including, The above test pad is, A base film divided into a first region and a second region; and A conductive layer located on the first region; comprising, The entire outer surface of the second region is surrounded by the first region on a plane, and A chip-on-film package characterized in that the second region includes a polygonal shape extended along the second direction.
In paragraph 8, A chip-on-film package characterized in that the conductive layer comprises a first conductive layer located on the first region and a second conductive layer in contact with the first conductive layer.
In Paragraph 9, At least one of the first conductive layer and the second conductive layer located in the first region surrounds the second region in a planar manner, A chip-on-film package characterized by the base film being exposed in the second region.
In Paragraph 9, A chip-on-film package characterized by having a groove formed in the second region, wherein the side is defined by at least one of the first conductive layer and the second conductive layer located in the first region and the bottom is defined by the base film.
In paragraph 8, The above test pad is, A chip-on-film package characterized by further including an insulating member located on the conductive layer in the first region.
In Paragraph 12, A chip-on-film package characterized by having a groove formed in the second region, wherein the side is defined by an insulating member located in the first region and the bottom is defined by at least one of a first conductive layer and a second conductive layer located in the second region.
In Paragraph 12, A chip-on-film package characterized in that the insulating member extends along a first direction in which the wiring structure is extended, covers at least a portion of the wiring structure, and includes a solder resist.
In paragraph 8, The conductive layer comprises a first conductive layer located on the first region and a second conductive layer in contact with the first conductive layer. The above wiring structure includes a first wiring pattern layer located on a base film and a second wiring pattern layer located on the first wiring pattern layer, and A chip-on-film package characterized in that the first wiring pattern layer and the first conductive layer are integrally formed, and the second wiring pattern layer and the second conductive layer are integrally formed.

Description

Test Pad and Chip On Film Package Including the Same This specification relates to a test pad and a chip-on-film package including the same. Driven by the recent development of the flat panel display industry, such as LCDs, the manufacturing industry for tape packages, which are driver IC components for flat panel displays, is also advancing. These tape packages are semiconductor packages utilizing a base film and can be divided into tape carrier packages (TCP) and chip-on-film (COF) packages. Generally, tape packages utilize a TAB method that uses input/output wiring patterns formed on a base film as external connection terminals, and mount the input/output wiring patterns by directly attaching them to a printed circuit board (PCB) or a display panel. In the manufacturing process of a tape package, an inspection process is performed to inspect the electrical characteristics of a driving integrated circuit mounted on a base film. Specifically, probe needles of a probe card contact conductive layers formed on the base film to inspect the driving integrated circuits. The conductive layers are electrically connected to input/output wiring patterns through connection leads. The conductive layers are spaced apart from each other by a certain distance, and the probe needles come into contact with the corresponding conductive layers. Recently, as the number of input and output wiring patterns in driving integrated circuits increases, the size of the base film on which the driving integrated circuit is mounted and the line width of the wiring patterns are gradually decreasing. FIG. 1 is a perspective view showing a display device according to one embodiment of the present invention. FIG. 2 is a plan view of a chip-on-film package according to one embodiment of the present invention. Figure 3 is a cross-sectional view along I-I' of Figure 2. FIG. 4 is a plan view of a test pad according to one embodiment of the present invention. Figure 5 is a cross-sectional view according to II-II' of Figure 4. FIG. 6 is a diagram showing the testing process of a chip-on-film package according to one embodiment of the present invention. FIG. 7 is a plan view of a chip-on-film package according to another embodiment of the present invention. Figure 8 is a cross-sectional view along III-III' of Figure 7. FIG. 9 is a plan view of a test pad according to another embodiment of the present invention. FIG. 10 is a cross-sectional view along IV-IV' of FIG. 9. FIGS. 11a to 11c are plan views of a test pad according to another embodiment of the present invention. Throughout the specification, identical reference numbers denote substantially identical components. In the following description, detailed descriptions of components and functions known in the art may be omitted if they are not related to the core components of the invention. The meanings of the terms described in this specification should be understood as follows. The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the depicted details. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing the present invention, if it is determined that a detailed description of related known technology may unnecessarily obscure the essence of the present invention, such detailed description is omitted. Where terms such as 'comprising,' 'having,' 'consisting of,' etc. are used in this specification, other parts may be added unless 'only' is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise. In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement. Although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention. The term “at least one” should be understood to include all combinations that can be presented from one or more related items. For example, the meaning of “at least one of th