KR-102964299-B1 - SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

Abstract

A memory system according to an embodiment of the present invention includes: a memory controller that generates a first target address by sampling an address according to an active command and provides the active command, a precharge command, a normal refresh command, the address, and the first target address; and a memory device that generates a first target refresh command according to the precharge command and the address, and refreshes a word line corresponding to the first target address according to the first target refresh command.

Inventors

• 김웅래

Assignees

• 에스케이하이닉스 주식회사

Dates

Publication Date

20260513

Application Date

20220103

Claims (20)

1. A memory controller that generates a first target address by sampling an address according to an active command, and provides the active command, a precharge command, a normal refresh command, the address, and the first target address; and A memory device that generates a first target refresh command according to the precharge command and a specific bit of the address, and refreshes a word line corresponding to the first target address according to the first target refresh command. A memory system including
2. In Article 1, The above memory controller is, A memory system that provides the address or the first target address together with the active command.
3. In Article 2, The above memory controller is, A memory system that provides a specific bit of the address as a high bit along with the precharge command after a certain period of time from the time when the first target address is provided along with the active command.
4. In Paragraph 3, The above schedule time is, A memory system corresponding to the time (tRAS, row address strobe minimum time) that must be secured to complete a read or write operation after an active operation.
5. In Article 1, The above memory device is, A memory system that samples the address according to the active command to generate a second target address, generates a second target refresh command according to the normal refresh command, and refreshes a word line corresponding to the second target address according to the second target refresh command.
6. In Article 5, The above memory device is, When the above precharge command is input, a specific bit of the above address is delayed for a predetermined time to generate the above first target refresh command, and A memory system that generates the second target refresh command whenever the number of inputs of the above normal refresh command reaches a predetermined number.
7. In Article 6, The above scheduled time is, A memory system corresponding to the time from precharge operation to active operation (tRP, precharge to active time).
8. In Article 1, The above memory controller is, A command issuance circuit that issues the normal refresh command whenever a counting value, which counts the number of inputs of the active command, reaches a predetermined value; A tracking circuit that generates the first target address by sampling the address according to the active command; and A scheduler that provides the address or the first target address together with the active command, provides the address together with the precharge command, and provides the normal refresh command. A memory system including
9. In Article 1, The above memory device is, A refresh command control circuit that generates the first target refresh command according to the precharge command and a specific bit of the address, generates the second target refresh command according to the normal refresh command, and generates the final target refresh command according to the first target refresh command or the second target refresh command; A refresh address control circuit that generates a second target address by randomly sampling the address according to the active command, selects one of the first target address or the second target address, and outputs it as a low-hammer address; and A row control circuit that refreshes one or more word lines corresponding to the row-hammer address according to the above final target refresh command. A memory system including
10. A refresh command control circuit that generates a first target refresh command according to a mode entry signal generated according to a precharge command and a specific bit of an address, generates a second target refresh command according to a normal refresh command, and generates a final target refresh command according to the first target refresh command or the second target refresh command; An active latch that latches the above address to an active address according to an active command; A refresh address control circuit that latches the active address according to the mode entry signal to generate a first target address, samples the active address at a random time to generate a second target address, selects one of the first target address or the second target address and outputs it as a low-hammer address; and A row control circuit that refreshes one or more word lines corresponding to the row-hammer address according to the above final target refresh command. A memory device including
11. In Article 10, The above refresh command control circuit is, A first command generation circuit that, when the above precharge command is input, generates the mode entry signal according to a specific bit of the above address, and delays the mode entry signal by a predetermined time to generate the first target refresh command; A second command generation circuit that generates the second target refresh command whenever the number of inputs of the above normal refresh command reaches a predetermined number; and A command output circuit that generates the final target refresh command according to the first target refresh command or the second target refresh command. A memory device including
12. In Article 11, The above-mentioned first command generation circuit is, A mode entry circuit that generates a mode entry signal according to a specific bit of the address when the above precharge command is input; and A timing control circuit that generates the first target refresh command by delaying the above mode entry signal by a scheduled time. A memory device including
13. In Article 12, The above mode entry circuit is, A mode latch that generates a mode enable signal by latching a specific bit of the address when the above precharge command is input; and A pulse generator that outputs the precharge command as the mode entry signal according to the above mode enable signal. A memory device including
14. In Article 12, The above timing control circuit is, It includes a plurality of flip-flops connected in series, and A memory device in which the number of the above-mentioned multiple flip-flops is set to correspond to the time from precharge operation to active operation (tRP, precharge to active time).
15. In Article 10, The above refresh address control circuit is, A section control circuit that generates a section selection signal defined by the above-mentioned mode entry signal and the above-mentioned final target refresh command; A first latch that latches the active address to the first target address according to the mode entry signal; A second latch that latches the active address to the second target address according to a sampling signal; A selection circuit that outputs a final target address by selecting one of the first target address or the second target address in response to the above interval selection signal; and An address output circuit that calculates the raw hammer address from the final target address and outputs the raw hammer address according to the final target refresh command. A memory device including
16. In Article 15, The above section control circuit is, A termination signal generation circuit that generates a mode termination signal activated according to the falling edge of the above final target refresh command; and A section definition circuit that generates the section selection signal, which is activated according to the mode entry signal and deactivated according to the mode exit signal. A memory device including
17. Refresh command control circuit that generates a target refresh command according to a mode entry signal generated according to a precharge command and an address; An active latch that latches the above address to an active address according to an active command; A refresh address control circuit that generates a target address by latching the active address according to the above mode entry signal; and Row control circuit that refreshes one or more word lines corresponding to the target address according to the above target refresh command A memory device that further includes
18. A step of latching the address to the active address according to the active command; A step of generating a mode entry signal according to a precharge command and a specific bit of the address; A step of generating a first target refresh command by delaying the above mode entry signal for a scheduled time; A step of generating a first target address by latching the active address according to the mode entry signal; and A step of refreshing one or more word lines corresponding to the first target address according to the first target refresh command. A method of operation of a memory device including
19. In Article 18, The step of generating the above mode entry signal is, When the above precharge command is input, a step of latching a specific bit of the address to generate a mode enable signal; and A step of outputting the precharge command as the mode entry signal according to the above mode enable signal. A method of operation of a memory device including
20. In Article 18, The above scheduled time is, A method of operation of a memory device corresponding to the time from precharge operation to active operation (tRP, precharge to active time).

Description

Semiconductor memory device and memory system including the same The present invention relates to semiconductor design technology, and specifically, the present invention relates to a memory system including a semiconductor memory device that performs target refresh. Recently, in addition to the normal refresh operation that sequentially refreshes multiple word lines, an additional refresh operation (hereinafter referred to as the “target refresh operation”) is performed on memory cells of a specific word line (hereinafter referred to as the “target word line”) that is highly likely to lose data due to the row hammering phenomenon. The row hammering phenomenon refers to a phenomenon in which data in memory cells connected to the target word line or adjacent word lines is damaged due to a high number of activations of a specific word line. To prevent such row hammering phenomena, a target refresh operation is performed on the target word line or adjacent word lines of the target word line that are activated more than a predetermined number of times. FIG. 1 is a block diagram of a memory system according to an embodiment of the present invention. Figure 2 is a detailed configuration diagram of the memory controller of Figure 1. Figure 3 is a detailed configuration diagram of the memory device of Figure 1. Figure 4 is a detailed block diagram of the refresh command control circuit of Figure 3. Figure 5 is a detailed circuit diagram of the mode entry circuit of Figure 4. Figure 6 is a detailed circuit diagram of the timing control circuit of Figure 4. Figure 7 is a detailed block diagram of the refresh address control circuit of Figure 3. Figure 8 is a detailed block diagram of the section control circuit of Figure 7. FIG. 9 is a timing diagram for explaining the operation of a memory device according to an embodiment of the present invention. FIGS. 10 and FIGS. 11 are flowcharts for explaining the operation of a memory device according to an embodiment of the present invention. Hereinafter, in order to explain in detail enough for a person skilled in the art to easily implement the technical concept of the present invention, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, throughout the specification, when a part is described as being "connected" to another part, this includes not only cases where they are "directly connected" but also cases where they are "electrically connected" with an intermediate circuit in between. Additionally, when a part is described as "including" or "equipped" with a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include or be equipped with additional components. Moreover, it will be understood that even if some components are described in the singular form throughout the specification, the present invention is not limited thereto, and such components may be composed of multiple units. In order to focus on explaining the refresh operation, the following embodiments will omit the description of the configuration related to the data input/output operation and focus on explaining the row control operation. FIG. 1 is a block diagram of a memory system (10) according to an embodiment of the present invention. Referring to FIG. 1, the memory system (10) may include a memory controller (100) and a semiconductor memory device (200). The memory controller (100) controls the overall operation of the memory system (10) and can control the overall data exchange between a host (not shown) and a memory device (200). The memory controller (100) can generate a command/address signal (C/A) in response to a request (REQ) from the host and provide it to the memory device (200). The memory controller (100) can provide a clock (CK) to the memory device (200) along with the command/address signal (C/A). The memory controller (100) can provide data (DQ) corresponding to host data (HDATA) provided from the host to the memory device (200) along with a data strobe signal (DQS). The memory controller (100) can receive data (DQ) read from the memory device (200) along with the data strobe signal (DQS) and provide it to the host as host data (HDATA). More specifically, the memory controller (100) may include a host interface (110), a processor (120), a refresh control module (130), a scheduler (140), and a memory interface (150). The host interface (110) may be configured to communicate with a host connected to the memory system (10) under the control of the processor (120). For example, the host interface (110) may receive a request (REQ) and host data (HDATA) from the host (20), and may receive data (DQ) read from the memory device (200) from the memory interface (150) and output it to the host (20) as host data (HDATA). The processor (120) can perform various operations to control the memory device (200) or perform firmware. The processor (120) can receive a request (REQ) a