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KR-102964328-B1 - VERTICAL SEMICONDUCTOR DEVICES

KR102964328B1KR 102964328 B1KR102964328 B1KR 102964328B1KR-102964328-B1

Abstract

A vertical semiconductor device comprises lower circuit patterns provided on a first substrate. A bonding film is provided on the lower circuit patterns. Wiring is provided on the bonding film. A cell stacking structure is provided on the wiring. A base pattern is provided on the cell stacking structure. An upper insulating film is provided on the base pattern. A cell contact plug is provided that penetrates the cell stacking structure and extends to the upper insulating film. A through-hole is provided that penetrates the outer side of the base pattern and extends to the upper insulating film. The cell contact plug and the through-hole include a barrier metal pattern and a metal pattern, and the barrier metal pattern is provided along the sidewalls and bottom surfaces of the cell contact hole and the through-hole.

Inventors

  • 김재호
  • 양우성
  • 구지모
  • 성석강
  • 이아름

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260513
Application Date
20220706

Claims (10)

  1. Lower circuit patterns formed on the first substrate; A bonding film provided on the lower circuit patterns above; Wiring provided on the bonding film above; Pattern structures provided on the wiring, wherein an insulating pattern and a gate electrode are alternately stacked in a vertical direction on the upper surface of the first substrate, and the edge portions have a stepped shape in which the length gradually increases from the bottom to the top, and extend in a first direction parallel to the upper surface of the first substrate; A buried insulation pattern provided within a trench between the above pattern structures and extending in the first direction; A base pattern provided on the above pattern structure; Upper insulating film on the above base pattern; A channel structure provided within a channel hole penetrating the above pattern structure and extending to the base pattern; A cell contact plug provided within a cell contact hole penetrating a stepped portion of the pattern structure, extending to the upper insulating film, and electrically connected to one gate electrode within the pattern structure; and It includes a through plug provided within a through hole that penetrates the outer side of the base pattern and extends to the upper insulating film, and A vertical semiconductor device in which the bottom surface of the cell contact plug and the through plug is positioned higher than the bottom surface of the buried insulation pattern.
  2. A vertical semiconductor device according to claim 1, wherein the trench, channel hole, cell contact hole, and through hole have side wall slopes such that they have a wider width from the bottom to the top, and each of the trench, channel hole, cell contact hole, and through hole has a folded portion on its side wall.
  3. A vertical semiconductor device in which, in claim 2, the bent portions of each of the trench, channel hole, cell contact hole and through hole are located on the same plane as each other.
  4. A vertical semiconductor device according to claim 1, wherein the cell contact plug and the through plug each include the same metal pattern, and the metal pattern includes a seam.
  5. In claim 1, the cell contact plug and the through plug include a barrier metal pattern and a metal pattern, and the barrier metal pattern is a vertical semiconductor device provided along the side wall and bottom surface of the cell contact hole and the through hole.
  6. A vertical semiconductor device according to claim 1, further comprising a plate contact plug provided within a plate contact hole penetrating the outer side of the pattern structure and electrically connected to the base pattern.
  7. In claim 6, the bottom surfaces of the cell contact plug, through plug, and plate contact plug are located in the same plane of the vertical semiconductor device.
  8. In claim 6, the plate contact plug is a vertical semiconductor device that penetrates the base pattern and contacts the upper insulating film.
  9. In claim 6, the plate contact plug is a vertical semiconductor device that does not penetrate the base pattern and contacts the bottom surface of the base pattern.
  10. A vertical semiconductor device according to claim 1, wherein the uppermost portion of the cell contact plug and the through plug has a slope such that the width decreases from the top to the bottom.

Description

Vertical Semiconductor Devices The present invention relates to a semiconductor device. More specifically, it relates to a bonding-type vertical semiconductor device. A bonded vertical semiconductor device can be formed by bonding a first substrate having peripheral circuits formed thereon and a second substrate having memory cells stacked vertically formed thereon. In the bonded vertical semiconductor device, as the stacking height of the memory cells increases, the vertical height of the wiring may also increase. Therefore, it is not easy to form the wiring. FIG. 1 is a schematic diagram illustrating an electronic system including a semiconductor device according to exemplary embodiments. FIG. 2 is a schematic perspective view for illustrating an electronic system including a semiconductor device according to an exemplary embodiment. FIG. 3 is a schematic cross-sectional view illustrating a semiconductor package including a semiconductor device according to an exemplary embodiment. FIGS. 4 to 21 are cross-sectional and plan views illustrating a method for manufacturing a vertical semiconductor device according to exemplary embodiments. FIGS. 22 to 25 are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to exemplary embodiments. FIGS. 26 to 28 are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to exemplary embodiments. FIG. 29 is a cross-sectional view showing a vertical semiconductor device according to exemplary embodiments. FIGS. 30 and 31 are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to exemplary embodiments. FIG. 32 is a cross-sectional view showing a vertical semiconductor device according to exemplary embodiments. FIG. 33 is a cross-sectional view showing a vertical semiconductor device according to exemplary embodiments. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. In the following description, a direction parallel to the surface of the substrate is referred to as the first direction, and a direction parallel to the surface of the substrate and perpendicular to the first direction is referred to as the second direction. Additionally, a direction perpendicular to the surface of the substrate is referred to as the perpendicular direction. FIG. 1 is a schematic diagram illustrating an electronic system including a semiconductor device according to exemplary embodiments. Referring to FIG. 1, the electronic system (1000) may include a semiconductor device (1100) and a controller (1200) electrically connected to the semiconductor device (1100). The electronic system (1000) may be a storage device or an electronic device including a storage device, comprising one or more semiconductor devices (1100). For example, the electronic system (1000) may be a Solid State Drive (SSD) device, a Universal Serial Bus (USB), a computing system, a medical device, or a communication device, comprising one or more semiconductor devices (1100). The semiconductor device (1100) may be a non-volatile memory device and, for example, any one of the vertical semiconductor devices shown in FIGS. 21, 28, 29 and FIGS. 32 to 33. The semiconductor device (1100) may include a first structure (1100F) and a second structure (1100S) on the first structure (1100F). The first structure (1100F) may be a peripheral circuit structure including a decoder circuit (1110), a page buffer (1120), and a logic circuit (1130). The second structure (1100S) may be a memory cell structure comprising a bit line (BL), a common source line (CSL), word lines (WL), first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and memory cell strings (CSTR) between the bit line (BL) and the common source line (CSL). In the second structure (1100S), each memory cell string (CSTR) may include lower transistors (LT1, LT2) adjacent to a common source line (CSL), upper transistors (UT1, UT2) adjacent to a bit line (BL), and a plurality of memory cell transistors (MCT) disposed between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of lower transistors (LT1, LT2) and the number of upper transistors (UT1, UT2) may vary depending on the embodiments. In exemplary embodiments, the upper transistors (UT1, UT2) may include string select transistors, and the lower transistors (LT1, LT2) may include ground select transistors. The lower gate lines (LL1, LL2) may each be the gate electrodes of the lower transistors (LT1, LT2). The word lines (WL) may be the gate electrodes of the memory cell transistors (MCT), and the upper gate lines (UL1, UL2) may each be the gate electrodes of the upper transistors (UT1, UT2). In exemplary embodiments, the lower transistors (LT1, LT2) may include a lower erase control transistor (LT1) and a ground select transistor (LT2) c