KR-102964332-B1 - DISPLAY DEVICE AND LEVEL SHIFTER

Abstract

Embodiments of the present disclosure relate to a display device and a level shifter, and more specifically, may provide a level shifter comprising: a clock generation circuit that generates a reference clock by receiving a timing control signal from a timing controller for controlling a gate driving circuit and a data driving circuit connected to a display panel; an output circuit that generates a gate clock for controlling the gate driving circuit in response to the reference clock; and a level control circuit that controls the level of the reference clock and the level of the gate clock according to a current flowing through the output channel of the gate clock.

Inventors

• 장원용
• 황태섭

Assignees

• 엘지디스플레이 주식회사

Dates

Publication Date

20260512

Application Date

20221216

Claims (18)

1. delete
2. A display panel comprising a plurality of gate lines, a plurality of data lines, and a plurality of subpixels; A gate driving circuit for driving the above plurality of gate lines; A data driving circuit for driving the above plurality of data lines; A level shifter for controlling the gate driving circuit above; and A timing controller that controls the level shifter and the data driving circuit, comprising: The above level shifter A clock generation circuit that generates a reference clock from a timing control signal supplied by the above timing controller; An output circuit that generates a gate clock for controlling the gate driving circuit in response to the above reference clock; and A level control circuit that controls the level of the reference clock and the level of the gate clock according to the current flowing in the output channel of the gate clock, wherein The above clock generation circuit is A first comparator that receives the on-clock among the timing control signals as an inverting input terminal and receives a first reference voltage as a non-inverting input terminal to output a first reference clock; and A display device comprising a second comparator that receives an off-clock among the above timing control signals as an inverting input terminal and receives a second reference voltage as a non-inverting input terminal to output a second reference clock.
3. In Article 2, The above first comparator The gate low voltage is applied as a negative power source, and A display device to which a high-potential variable voltage is applied as a positive power source.
4. In Article 2, The above second comparator The gate low voltage is applied as a negative power source, and A display device to which a high-potential variable voltage is applied as a positive power source.
5. In Article 2, The above output circuit is A pull-up transistor in which the above-mentioned first reference clock is applied to the gate node and a high-potential variable voltage is applied to the drain node; A pull-down transistor to which the second reference clock is applied to the gate node and a gate low voltage is applied to the drain node; and A display device comprising an output resistor connected to the source node of the pull-up transistor and the source node of the pull-down transistor, to which the gate clock is output.
6. In Article 5, The above-mentioned first reference clock and the above-mentioned second reference clock are A display device applied in common to multiple output circuits.
7. A display panel comprising a plurality of gate lines, a plurality of data lines, and a plurality of subpixels; A gate driving circuit for driving the above plurality of gate lines; A data driving circuit for driving the above plurality of data lines; A level shifter for controlling the gate driving circuit above; and A timing controller that controls the level shifter and the data driving circuit, comprising: The above level shifter A clock generation circuit that generates a reference clock from a timing control signal supplied by the above timing controller; An output circuit that generates a gate clock for controlling the gate driving circuit in response to the above reference clock; and A level control circuit that controls the level of the reference clock and the level of the gate clock according to the current flowing in the output channel of the gate clock, wherein The above level control circuit is A feedback comparator in which the gate clock is applied to an inverting input terminal and an overcurrent reference voltage is applied to a non-inverting input terminal; A first level resistor and a second level resistor connected in series between the gate high voltage and ground; A first level transistor in which the output signal of the feedback comparator is applied to the gate node, the gate high voltage is applied to the drain node, and a high potential variable voltage is output through the source node; and A display device comprising a second level transistor in which the output signal of the feedback comparator is applied to a gate node, the drain node is connected between the first level resistor and the second level resistor, and the high potential variable voltage is output through a source node.
8. In Article 7, The above first-level transistor is a P-type transistor, and The above second-level transistor is an N-type transistor in a display device.
9. In Article 7, The above first level resistor and the above second level resistor are A display device determined to change the brightness of the display panel by the high potential variable voltage while the display panel maintains operation.
10. delete
11. A clock generation circuit that generates a reference clock by receiving a timing control signal from a timing controller for controlling a gate driving circuit and a data driving circuit connected to a display panel; An output circuit that generates a gate clock for controlling the gate driving circuit in response to the above reference clock; and A level control circuit that controls the level of the reference clock and the level of the gate clock according to the current flowing in the output channel of the gate clock, wherein The above clock generation circuit is A first comparator that receives an on-clock among the above timing control signals as an inverting input terminal and a first reference voltage as a non-inverting input terminal to output a first reference clock; and A level shifter comprising a second comparator that receives an off-clock among the above timing control signals as an inverting input terminal and receives a second reference voltage as a non-inverting input terminal to output a second reference clock.
12. In Article 11, The above first comparator The gate low voltage is applied as a negative power source, and A level shifter to which a high-potential variable voltage is applied as a positive power source.
13. In Article 11, The above second comparator The gate low voltage is applied as a negative power source, and A level shifter to which a high-potential variable voltage is applied as a positive power source.
14. In Article 11, The above output circuit is A pull-up transistor in which the above-mentioned first reference clock is applied to the gate node and a high-potential variable voltage is applied to the drain node; A pull-down transistor to which the second reference clock is applied to the gate node and a gate low voltage is applied to the drain node; and A level shifter comprising an output resistor connected to the source node of the pull-up transistor and the source node of the pull-down transistor, to which the gate clock is output.
15. In Article 14, The above-mentioned first reference clock and the above-mentioned second reference clock are A level shifter applied commonly to multiple output circuits.
16. A clock generation circuit that generates a reference clock by receiving a timing control signal from a timing controller for controlling a gate driving circuit and a data driving circuit connected to a display panel; An output circuit that generates a gate clock for controlling the gate driving circuit in response to the above reference clock; and A level control circuit that controls the level of the reference clock and the level of the gate clock according to the current flowing in the output channel of the gate clock, wherein The above level control circuit is A feedback comparator in which the gate clock is applied to an inverting input terminal and an overcurrent reference voltage is applied to a non-inverting input terminal; A first level resistor and a second level resistor connected in series between the gate high voltage and ground; A first level transistor to which the output signal of the feedback comparator is applied to the gate node, the gate high voltage is applied to the drain node, and a high potential variable voltage is output through the source node; and A level shifter comprising a second level transistor in which the output signal of the feedback comparator is applied to a gate node, the drain node is connected between the first level resistor and the second level resistor, and the high potential variable voltage is output through a source node.
17. In Article 16, The above first-level transistor is a P-type transistor, and The above second level transistor is a level shifter that is an N-type transistor.
18. In Article 16, The above first level resistor and the above second level resistor are A level shifter determined to change the brightness of the display panel by the high potential variable voltage while the display panel maintains operation.

Description

Display Device and Level Shifter The embodiments of the present disclosure relate to a display device and a level shifter, and more specifically, to a display device and a level shifter capable of preventing accidents caused by an error in a display panel. As the information society develops, there is an increasing demand for display devices that display images, and various types of display devices, such as liquid crystal displays and organic light-emitting displays, are being utilized. Among these display devices, organic light-emitting display devices utilize self-emissive organic light-emitting diodes, offering fast response speeds and advantages in contrast ratio, luminous efficiency, brightness, and viewing angle. The display device includes a light-emitting element placed in each of a plurality of subpixels arranged on a display panel, and can display an image by controlling the brightness represented by each subpixel by emitting light through voltage control flowing through the light-emitting element. Recently, the scope of application for display devices is gradually expanding, including not only portable computers but also desktop computer monitors, automotive displays, and wall-mounted televisions. Such display devices can provide various functions depending on the application of the electronic device in which the display panel is mounted; for example, in the case of automotive display devices, navigation is an essential function. Meanwhile, during the operation of the display device, an overcurrent may flow through the display panel due to shock or cracks. In this case, if the display device is operating in real time, such as with a navigation function, the display operation may be cut off due to the overcurrent, and there is a possibility that an accident may occur due to the sudden screen shutdown. FIG. 1 is a schematic diagram showing a display device according to embodiments of the present disclosure. FIG. 2 is a system example drawing of a display device according to embodiments of the present disclosure. FIG. 3 is a diagram illustrating an example of a display panel in which a gate driving circuit is implemented as a gate-in panel type in a display device according to embodiments of the present disclosure. FIG. 4 is a diagram illustrating an example of a subpixel circuit of a display device according to embodiments of the present disclosure. FIG. 5 is a diagram illustrating the connection relationship of a level shifter in a display device according to embodiments of the present disclosure. FIG. 6 is a signal waveform diagram showing the input and output signals of a level shifter in a display device according to embodiments of the present disclosure. FIG. 7 is a block diagram showing the configuration of a level shifter in a display device according to embodiments of the present disclosure. FIG. 8 is a diagram showing an example of a clock generation circuit included in a level shifter in a display device according to embodiments of the present disclosure. FIG. 9 is a drawing showing an example of an output circuit included in a level shifter in a display device according to embodiments of the present disclosure. FIG. 10 is a drawing showing an example of a level control circuit included in a level shifter in a display device according to embodiments of the present disclosure. FIG. 11 is a diagram illustrating an example of the circuit configuration of a level shifter in a display device according to embodiments of the present disclosure. FIG. 12 is a signal waveform diagram showing the operation of a level shifter when an overcurrent occurs in a display device according to embodiments of the present disclosure. FIG. 13 is a drawing showing examples of cases in a display device according to embodiments of the present disclosure in which operation is blocked by impact or the like on the display panel and in cases where operation is maintained while reducing the brightness of the screen. Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the exemplary drawings. In assigning reference numerals to the components of each drawing, the same components may have the same reference numeral as much as possible, even if they are shown in different drawings. Furthermore, in describing the present disclosure, if it is determined that a detailed description of related known components or functions may obscure the essence of the present disclosure, such detailed description may be omitted. Where terms such as "comprising," "having," or "consisting of" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it may include a plural unless otherwise specified. Additionally, terms such as first, second, A, B, (a), (b), etc., may be used to describe the components of the present disclosure. These terms are used merely to distinguish the components from other components, and the nature, ord