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KR-102964562-B1 - SEMICONDUCTOR PACKAGE

KR102964562B1KR 102964562 B1KR102964562 B1KR 102964562B1KR-102964562-B1

Abstract

A semiconductor package is provided. The semiconductor package comprises an insulating layer including a first surface and a second surface facing each other, a wiring area and a via area disposed within the insulating layer, and a redistribution pattern including the wiring area and the wiring area disposed on the via area, and a first semiconductor chip connected to the redistribution pattern on the redistribution pattern, wherein the upper surface of the wiring area is disposed on the same plane as the first surface of the insulating layer.

Inventors

  • 이주형
  • 박기태
  • 박병률
  • 오준석
  • 윤종호

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260512
Application Date
20200609

Claims (10)

  1. An insulating layer comprising a first surface and a second surface facing each other; A redistribution pattern comprising a wiring area and a via area disposed within the insulating layer, wherein the wiring area is a redistribution pattern disposed on the via area; A first semiconductor chip connected to the redistribution pattern on the first surface of the insulating layer and the redistribution pattern; On the second surface of the insulating layer, a passivation layer; An under-bump metal layer comprising a UBM via disposed within the passivation layer and connected to the redistribution pattern, and a UBM pad disposed on the UBM via; and On the above passivation layer, a solder ball in contact with the UBM pad is included, The upper surface of the above redistribution pattern is disposed on the same plane as the first surface of the insulation layer, and The lower surface of the above-mentioned redistribution pattern is disposed on the same plane as the second surface of the above-mentioned insulating layer, and The upper surface of the above under-bump metal layer is positioned on the same plane as the upper surface of the above passivation layer, and The lower surface of the above-mentioned under-bump metal layer is disposed on the same plane as the lower surface of the above-mentioned passivation layer, and The above redistribution pattern includes first and second side walls facing each other, and The first sidewall of the above redistribution pattern and the second sidewall of the above redistribution pattern each extend in the thickness direction of the insulating layer, and The above under-bump metal layer includes third and fourth side walls facing each other, and The third sidewall of the under-bump metal layer and the fourth sidewall of the under-bump metal layer extend in the thickness direction of the passivation layer, and The first sidewall of the above-mentioned redistribution pattern, the second sidewall of the above-mentioned redistribution pattern, the third sidewall of the under-bump metal layer, and the fourth sidewall of the under-bump metal layer are semiconductor packages that do not have a step.
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  5. In Article 1, The above wiring region is a semiconductor package disposed on the upper surface of the above via region.
  6. In Article 1, A semiconductor package further comprising a molding layer disposed on the first surface of the insulating layer and covering at least a portion of the first semiconductor chip, and a through-via that penetrates the molding layer and is connected to the redistribution pattern.
  7. A rewiring pattern comprising a via region and a wiring region disposed on the via region; An insulating layer comprising a via trench in which the via region is disposed and a wiring trench in which the wiring region is disposed, as a single layer; A semiconductor chip disposed on the upper surface of the above-mentioned redistribution pattern and the above-mentioned insulating layer and connected to the above-mentioned redistribution pattern; An under-bump metal layer comprising a UBM via connected to the redistribution pattern and a UBM pad disposed on the UBM via, on the lower surface of the insulating layer; A passivation layer comprising, as a single layer, a UBM via trench in which the UBM via is disposed and a UBM pad trench in which the UBM pad is disposed; and On the above passivation layer, a solder ball connected to and in contact with the UBM pad is included, The above via trench includes first and second sidewalls facing each other, and The above wiring trench includes third and fourth side walls facing each other, and The upper surface of the above redistribution pattern is positioned on the same plane as the upper surface of the insulation layer, and The lower surface of the above-mentioned redistribution pattern is disposed on the same plane as the lower surface of the above-mentioned insulating layer, and The upper surface of the above under-bump metal layer is positioned on the same plane as the upper surface of the above passivation layer, and The lower surface of the above-mentioned under-bump metal layer is disposed on the same plane as the lower surface of the above-mentioned passivation layer, and The first sidewall of the via trench and the third sidewall of the wiring trench are aligned on the same line, and the second sidewall of the via trench and the fourth sidewall of the wiring trench are aligned on the same line, A semiconductor package in which the side walls of the above UBM via trench are each directly connected to the side walls of the above UBM pad trench, and the side walls of the above UBM via trench are each placed on the same line as the side walls of the above UBM pad trench.
  8. In Article 7, A semiconductor package further comprising, between the above-mentioned redistribution pattern and the above-mentioned insulating layer, a bottom surface connecting the first and second sidewalls of the via trench and the first and second sidewalls, and a bottom surface connecting the third and fourth sidewalls of the wiring trench and the third and fourth sidewalls.
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  10. A redistribution structure comprising a first surface and a second surface facing each other; On the second surface of the redistribution structure, a core layer comprising a core wiring layer, a core insulating layer surrounding the core wiring layer, and a cavity exposing at least a portion of the second surface of the redistribution structure; A semiconductor chip disposed within the cavity of the core layer and connected to the redistribution structure; and It includes a solder ball disposed on the first surface of the above-mentioned redistribution structure, and The above redistribution structure is, A first insulating layer and, A first redistribution pattern comprising a first via region and a first wiring region disposed within the first insulating layer, wherein the first via region is disposed on the first wiring region and is connected to the semiconductor chip, and A second insulating layer disposed on the first insulating layer, and A second redistribution pattern comprising a second via region and a second wiring region disposed within the second insulating layer, wherein the second via region is disposed on the second wiring region and is connected to the first wiring region, and A passivation layer disposed on the second insulating layer above, and It includes an under-bump metal layer disposed within the passivation layer and comprising a UBM via connected to the second wiring region and a UBM pad in contact with the solder ball, and In the direction from the second surface toward the first surface, the upper surface of the first redistribution pattern is disposed on the same plane as the upper surface of the first insulating layer, and the lower surface of the first redistribution pattern is disposed on the same plane as the lower surface of the first insulating layer, and In the direction from the second surface toward the first surface, the upper surface of the second redistribution pattern is disposed on the same plane as the upper surface of the second insulating layer, and the lower surface of the second redistribution pattern is disposed on the same plane as the lower surface of the second insulating layer, and In the direction from the second surface toward the first surface, the upper surface of the under-bump metal layer is disposed on the same plane as the upper surface of the passivation layer, and the lower surface of the under-bump metal layer is disposed on the same plane as the lower surface of the passivation layer, The first insulating layer, the second insulating layer, and the passivation layer are single layers and include a photosensitive insulating material, The above-mentioned first redistribution pattern includes first and second side walls facing each other, and The above second redistribution pattern includes third and fourth side walls facing each other, and The above under-bump metal layer includes fifth and sixth side walls facing each other, and The first sidewall of the first redistribution pattern and the second sidewall of the first redistribution pattern each extend in the thickness direction of the first insulating layer, and The third sidewall of the second redistribution pattern and the fourth sidewall of the second redistribution pattern each extend in the thickness direction of the second insulating layer, and The fifth sidewall of the under-bump metal layer and the sixth sidewall of the under-bump metal layer are each extended in the thickness direction of the passivation layer, and The first sidewall of the first rewiring pattern, the second sidewall of the first rewiring pattern, the third sidewall of the second rewiring pattern, the fourth sidewall of the second rewiring pattern, the fifth sidewall of the under-bump metal layer, and the sixth sidewall of the under-bump metal layer are semiconductor packages that do not have a step.

Description

Semiconductor Package The present invention relates to a semiconductor package. Semiconductor packaging is a process of packaging a semiconductor chip (or semiconductor die) to electrically connect it to an electronic device. As the size of semiconductor chips decreases, semiconductor packages have been proposed that utilize a redistribution layer to place I/O terminals on the outside of the semiconductor chip. For example, Fan-In Wafer Level Package (FIWLP), Fan-Out Wafer Level Package (FOWLP), and Fan-Out Panel Level Package (FOPLP) types have been proposed. Meanwhile, the redistribution layer includes wiring regions and via regions and is formed through a photolithography process. During the process, it is necessary to align the wiring regions and via regions. FIG. 1 is a drawing for illustrating a semiconductor package according to some embodiments of the present invention. FIG. 2 is a drawing for illustrating a semiconductor package according to some other embodiments of the present invention. FIG. 3 is a drawing for illustrating a semiconductor package according to some other embodiments of the present invention. FIG. 4 is a drawing for illustrating a semiconductor package according to some other embodiments of the present invention. Figure 5 is an enlarged view of the S1 region of Figure 4. Figure 6 is an enlarged view of the S2 region of Figure 4. Figure 7 is an enlarged view of the S3 area of Figure 4. FIGS. 8 to 14 are intermediate step drawings for explaining a method for manufacturing a semiconductor package according to some embodiments of the present invention. FIGS. 15 and 16 are intermediate step drawings for illustrating a method of manufacturing a semiconductor package according to some other embodiments of the present invention. FIG. 17 is a drawing for illustrating a semiconductor package according to some other embodiments of the present invention. FIG. 18 is a drawing for illustrating a semiconductor package according to some other embodiments of the present invention. FIG. 19 is a drawing for illustrating a semiconductor package according to some other embodiments of the present invention. FIG. 20 is a drawing for illustrating a semiconductor package according to some other embodiments of the present invention. FIG. 1 is a drawing for illustrating a semiconductor package according to some embodiments of the present invention. Referring to FIG. 1, a semiconductor package according to some embodiments of the present invention may include a redistribution structure (100), an under-bump metal layer (140), a first passivation layer (145), a core layer (200), a first semiconductor chip (300), and a first molding layer (400). The redistribution structure (100) may include a plurality of redistribution patterns (110, 120, 130) and a plurality of insulating layers (115, 125, 135). The redistribution structure (100) may include, for example, a first redistribution pattern (110), a first insulating layer (115), a second redistribution pattern (120), a second insulating layer (125), a third redistribution pattern (130), and a third insulating layer (135). In the present drawing, the redistribution structure (100) is shown as comprising only three insulating layers (115, 125, 135) and three redistribution patterns (110, 120, 130), but this is exemplary and the number, location, or arrangement of the insulating layers (115, 12, 135) and redistribution patterns (110, 120, 130) may vary. The first to third insulating layers (115, 125, 135) may be a single layer. The first to third insulating layers (115, 125, 135) may each include a first surface (115a, 125a, 135a) and a second surface (115b, 125b, 135b) facing each other. For example, the first surface (115a, 125a, 135a) and the second surface (115b, 125b, 135b) may face each other in a first direction (DR1). The first surface (115a, 125a, 135a) may be an upper surface with respect to the first direction (DR1), and the second surface (115b, 125b, 135b) may be a lower surface with respect to the first direction (DR1). Here, the first direction (DR1) may be the thickness direction of the first to third insulating layers (115, 125, 135). The first to third insulating layers (115, 125, 135) can be stacked sequentially in the first direction (DR1). The second insulating layer (125) can be placed on the first surface (115a) of the first insulating layer (115), and the third insulating layer (135) can be placed on the first surface (125a) of the second insulating layer (125). The first surface (115a) of the first insulating layer (115) may be the second surface (125b) of the second insulating layer (125), and the first surface (125a) of the second insulating layer (125) may be the second surface (135b) of the third insulating layer (135). The first to third insulating layers (115, 125, 135) may contain the same material. For example, the first to third insulating layers (115, 125, 135) may contain a photosensitive insulating material (PID; Photo Imageable