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KR-102964583-B1 - SEMICONDUCTOR DEVICE

KR102964583B1KR 102964583 B1KR102964583 B1KR 102964583B1KR-102964583-B1

Abstract

The present invention relates to a semiconductor device, and more specifically, comprises: a first active pattern and a second active pattern on a substrate; a device isolation film filling a trench between the first and second active patterns; a first channel pattern and a second channel pattern provided respectively on the first and second active patterns, each of the first and second channel patterns comprising a plurality of stacked semiconductor patterns; and a gate electrode on the first and second channel patterns, wherein the device isolation film comprises a first portion and a second portion vertically overlapping with the gate electrode, the first portion being provided on the second portion, and the silicon (Si) concentration of the first portion may be greater than the silicon (Si) concentration of the second portion.

Inventors

  • 강승모
  • 김태곤
  • 김재문
  • 오재훈
  • 이선혜
  • 이시형
  • 이주리

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260513
Application Date
20220616

Claims (10)

  1. A first active pattern and a second active pattern on a substrate; A device isolation film that fills the trench between the first and second active patterns; A first channel pattern and a second channel pattern provided respectively on the first and second active patterns, each of the first and second channel patterns comprising a plurality of stacked semiconductor patterns; and Includes gate electrodes on the first and second channel patterns, The above-mentioned device isolation film includes a first portion and a second portion that overlap vertically with the gate electrode, and The above first part is provided on the above second part, and The silicon (Si) concentration of the first part is greater than the silicon (Si) concentration of the second part, and The center of the upper surface of the first part is flat, and the outer edge of the upper surface of the first part covers the side walls of the first and second active patterns, The above outer portion is a semiconductor device having a curved shape.
  2. In paragraph 1, A semiconductor device in which the silicon concentration of the first portion is 41 at% to 45 at%.
  3. In paragraph 2, A semiconductor device in which the silicon concentration of the second portion is 31 at% to 35 at%.
  4. delete
  5. delete
  6. In paragraph 1, The above-mentioned device isolation film is a semiconductor device comprising a silicon oxide film, a silicon oxynitride film, or a combination thereof.
  7. A first active pattern and a second active pattern on a substrate; A device isolation film that fills the trench between the first and second active patterns; A first channel pattern and a second channel pattern provided respectively on the first and second active patterns, each of the first and second channel patterns comprising a plurality of stacked semiconductor patterns; and Includes gate electrodes on the first and second channel patterns, The device isolation layer vertically superimposed with the gate electrode comprises a first portion having a silicon (Si) concentration of 41 at% to 45 at%, and The center of the upper surface of the first part is flat, and the outer edge of the upper surface of the first part covers the side walls of the first and second active patterns, The above outer part has a curved shape, A semiconductor device in which the level difference between the upper surface of each of the first and second active patterns and the upper surface of the first part is greater than 0 Å and less than or equal to 200 Å.
  8. In Paragraph 7, The above-mentioned device isolation film further comprises a second portion provided below the first portion, wherein A semiconductor device in which the concentration of silicon in the first part is greater than the concentration of silicon in the second part.
  9. A substrate including an active region; A device isolation film defining an active pattern on the active region, wherein the device isolation film comprises a first portion and a second portion interposed between adjacent active patterns, wherein the first and second portions are vertically superimposed such that the first portion is provided on the second portion, the center of the upper surface of the first portion is flat, the outer portion of the upper surface of the first portion covers the sidewall of the active pattern, and the outer portion has a curved shape; A channel pattern and a source/drain pattern on the active pattern, wherein the channel pattern comprises a plurality of semiconductor patterns vertically stacked and spaced apart from each other; A gate electrode on the plurality of semiconductor patterns, wherein the gate electrode includes a portion interposed between adjacent semiconductor patterns among the plurality of semiconductor patterns; A first gate insulating film between the mutually adjacent semiconductor patterns and the portion of the gate electrode, and a second gate insulating film covering the upper portion of the active pattern and the device isolation film; A gate capping pattern on the upper surface of the gate electrode; An interlayer insulating film on the gate capping pattern above; A gate contact that penetrates the interlayer insulating film and the gate capping pattern and is electrically connected to the gate electrode; A first metal layer on the interlayer insulating film, wherein the first metal layer comprises power wiring and first wiring electrically connected to the gate contact; and It includes a second metal layer on the first metal layer, The second metal layer includes second wirings electrically connected to the first metal layer, and A semiconductor device in which the silicon (Si) concentration in the first portion of the above-mentioned device isolation film is greater than the silicon (Si) concentration in the second portion.
  10. In Paragraph 9, A semiconductor device in which the silicon concentration of the first portion is 41 at% to 45 at%.

Description

Semiconductor Device The present invention relates to a semiconductor device, and more specifically, to a semiconductor device including a field-effect transistor. Semiconductor devices include integrated circuits composed of MOS (Metal Oxide Semiconductor) FETs. As the size and design rules of semiconductor devices gradually shrink, the scale-down of MOS FETs is also accelerating. The operating characteristics of semiconductor devices may degrade as the size of MOS FETs is reduced. Accordingly, various methods are being studied to form semiconductor devices with superior performance while overcoming the limitations associated with high integration of semiconductor devices. FIGS. 1 to 3 are conceptual diagrams for explaining logic cells of a semiconductor device according to embodiments of the present invention. FIG. 4 is a plan view for illustrating a semiconductor device according to embodiments of the present invention. FIGS. 5a to 5d are cross-sectional views along the lines A-A', B-B', C-C', and D-D' of FIG. 4, respectively. FIG. 6 is an enlarged view showing one embodiment of the M region of FIG. 5d. FIGS. 7a to 12c are cross-sectional views for explaining a method for manufacturing a semiconductor device according to embodiments of the present invention. FIGS. 13 to 16 are cross-sectional views illustrating a method for forming the device isolation film of FIG. 7b. FIGS. 1 to 3 are conceptual diagrams for explaining logic cells of a semiconductor device according to embodiments of the present invention. Referring to FIG. 1, a Single Height Cell (SHC) may be provided. Specifically, a first power line (M1_R1) and a second power line (M1_R2) may be provided on a substrate (100). The first power line (M1_R1) may be a channel for providing a source voltage (VSS), for example, a ground voltage. The second power line (M1_R2) may be a channel for providing a drain voltage (VDD), for example, a power voltage. A single height cell (SHC) may be defined between a first power line (M1_R1) and a second power line (M1_R2). The single height cell (SHC) may include a first active region (AR1) and a second active region (AR2). Either of the first and second active regions (AR1, AR2) may be a PMOSFET region, and the other of the first and second active regions (AR1, AR2) may be an NMOSFET region. In other words, the single height cell (SHC) may have a CMOS structure provided between the first power line (M1_R1) and the second power line (M1_R2). Each of the first and second active regions (AR1, AR2) may have a first width (W1) in the first direction (D1). The length of the single height cell (SHC) in the first direction (D1) may be defined as a first height (HE1). The first height (HE1) may be substantially equal to the distance (e.g., pitch) between the first power line (M1_R1) and the second power line (M1_R2). A single height cell (SHC) can constitute a single logic cell. In this specification, a logic cell may refer to a logic element that performs a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). That is, a logic cell may include transistors for constituting a logic element and wirings connecting said transistors to each other. Referring to FIG. 2, a Double Height Cell (DHC) may be provided. Specifically, a first power line (M1_R1), a second power line (M1_R2), and a third power line (M1_R3) may be provided on a substrate (100). The first power line (M1_R1) may be positioned between the second power line (M1_R2) and the third power line (M1_R3). The third power line (M1_R3) may be a passage through which a source voltage (VSS) is provided. A double height cell (DHC) may be defined between the second power wiring (M1_R2) and the third power wiring (M1_R3). The double height cell (DHC) may include two first active regions (AR1) and two second active regions (AR2). One of the two second active regions (AR2) may be adjacent to the second power wiring (M1_R2). The other of the two second active regions (AR2) may be adjacent to the third power wiring (M1_R3). Two first active regions (AR1) may be adjacent to the first power wiring (M1_R1). In a planar view, the first power wiring (M1_R1) may be positioned between the two first active regions (AR1). The length of the double height cell (DHC) in the first direction (D1) can be defined as the second height (HE2). The second height (HE2) may be approximately twice the first height (HE1) of FIG. 1. The two first active regions (AR1) of the double height cell (DHC) can be combined to operate as a single active region. In the present invention, the double height cell (DHC) shown in FIG. 2 may be defined as a multi-height cell. Although not illustrated, the multi-height cell may include a triple height cell in which the cell height is approximately three times that of a single height cell (SHC). Referring to FIG. 3, a first single height cell (SHC1), a second single height cell (SHC2), and a double height cell (DHC) may be arranged two-dimensionally on a substrate