KR-102964606-B1 - Positive and negative voltage charge pump circuits, chips, and communication terminals

KR102964606B1KR 102964606 B1KR102964606 B1KR 102964606B1KR-102964606-B1

Abstract

The present invention discloses positive and negative voltage charge pump circuits, a chip, and a communication terminal. The positive and negative voltage charge pump circuits include a clock generation module, a positive voltage charge pump module, a transient enhancement module, and a negative voltage charge pump module. Based on a clock signal output by the clock generation module, a positive voltage is generated through the positive voltage charge pump module, and at the same time, the positive voltage and power supply voltage are sampled using the transient enhancement module, converted into current, and then a comparison is performed. Based on the comparison result, a switchable input voltage is supplied to the negative voltage charge pump module, and the negative voltage charge pump module not only sets the negative voltage quickly and stably according to the clock signal output by the clock generation module, but also improves the speed and efficiency of generating the negative voltage by the negative voltage charge pump module and can flexibly implement different negative voltage requirements.

Inventors

왕 융서우
천 청
리 춘링
린 성

Assignees

상하이 반칩 테크놀러지스 컴퍼니 리미티드

Dates

Publication Date: 20260512
Application Date: 20211115
Priority Date: 20201116

Claims (15)

As a positive and negative voltage charge pump circuit, It includes a clock generation module, an anode voltage charge pump module, a transient enhancement module, and a cathode voltage charge pump module, wherein the output terminal of the clock generation module is connected to the input terminals of the anode voltage charge pump module and the cathode voltage charge pump module, the output terminal of the anode voltage charge pump module is connected to the input terminal of the transient enhancement module, the output terminal of the transient enhancement module is connected to the input power terminal of the cathode voltage charge pump module, and the power terminals of the clock generation module, the anode voltage charge pump module, and the transient enhancement module are all connected to a power supply voltage; An anode voltage charge pump module generates an anode voltage based on a clock signal output by a clock generation module, and the anode voltage and the power supply voltage are compared after being sampled by a transient enhancement module as an input voltage source and converted into current, and, depending on the comparison result, a switchable input voltage is supplied to the cathode voltage charge pump module so that the cathode voltage charge pump module generates a cathode voltage according to a clock signal output by the clock generation module.
In Article 1, The positive voltage charge pump module comprises a first clock conversion unit and at least one positive voltage charge pump unit, wherein the input terminal of the first clock conversion unit is connected to the output terminal of the clock generation module, and the output terminal of the first clock conversion unit is connected to the input terminal of each positive voltage charge pump unit, characterized in that the positive and negative voltage charge pump circuits are each connected to the input terminal of each positive voltage charge pump unit.
In Article 2, The first clock conversion unit comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first NAND gate, and a second NAND gate, wherein the input terminal of the first inverter is connected to the output terminal of the clock generation module and the input terminal of one of the second NAND gates, the output terminal of the first inverter is connected to the input terminal of the first NAND gate, the output terminal of the first NAND gate is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the first output terminal and the input terminal of the third inverter, the output terminal of the third inverter is connected to the other input terminal of the second NAND gate and the second output terminal, the output terminal of the second NAND gate is connected to the input terminal of the fourth inverter, the output terminal of the fourth inverter is connected to the fourth output terminal and the input terminal of the fifth inverter, and the output terminal of the fifth inverter is connected to the other input terminal of the first NAND gate and the third output terminal, characterized by an anode and cathode voltage charge pump. Circuit.
In Article 2, A positive and negative voltage charge pump circuit characterized in that, when using a plurality of the above positive voltage charge pump units, the input voltage of each of the above positive voltage charge pump units starts from the second positive voltage charge pump unit and is connected to the positive voltage output terminal of the preceding positive voltage charge pump unit.
In Article 4, The anode voltage charge pump unit comprises a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first capacitor, a second capacitor, and a third capacitor; the gate of the first NMOS transistor is connected to the fourth output terminal of the first clock conversion unit, the sources of the first NMOS transistor and the second NMOS transistor are each grounded, the drain of the first NMOS transistor is connected to one end of the second capacitor and the drain of the first PMOS transistor, respectively, the gate of the first PMOS transistor is connected to the second output terminal of the first clock conversion unit, the gate of the second NMOS transistor is connected to the first output terminal of the first clock conversion unit, the drain of the second NMOS transistor is connected to one end of the first capacitor and the drain of the second PMOS transistor, respectively, and the gate of the second PMOS transistor is connected to the first clock A positive and negative voltage charge pump circuit characterized by being connected to the third output terminal of a conversion unit, wherein the sources of the second PMOS transistor, the first PMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are all connected to an input voltage, the gate of the fourth NMOS transistor is respectively connected to the drain of the third NMOS transistor, the other end of the first capacitor, the gate of the fourth PMOS transistor, and the drain of the third PMOS transistor, and the gate of the third NMOS transistor is respectively connected to the drain of the fourth NMOS transistor, the other end of the second capacitor, the gate of the third PMOS transistor, and the drain of the fourth PMOS transistor, wherein the sources of the third PMOS transistor and the fourth PMOS transistor are all connected to one end of the third capacitor and the positive voltage output terminal, and the other end of the third capacitor is grounded.
In Article 5, The above transient enhancement module includes a voltage sampling comparison unit and a voltage switching unit, wherein the input terminal of the voltage sampling comparison unit is connected to the positive voltage output terminal of the positive voltage charge pump unit and the power supply voltage, and the output terminal of the voltage sampling comparison unit is connected to the input terminal of the voltage switching unit, characterized in that the positive and negative voltage charge pump circuits are.
In Article 6, The voltage sampling comparison unit comprises a first resistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a second resistor, a third resistor, and a fourth capacitor, wherein one end of the first resistor, the source of the fifth PMOS transistor, and the source of the sixth PMOS transistor are each connected to a power supply voltage, the other end of the first resistor is respectively connected to the drain and gate of the fifth NMOS transistor and the gate of the sixth NMOS transistor, and the drain of the sixth NMOS transistor is respectively connected to the drain and gate of the fifth PMOS transistor and the gate of the sixth PMOS transistor, and the drain of the sixth PMOS transistor is respectively connected to one end of the fourth capacitor, one end of the third resistor, the drain of the seventh NMOS transistor, and the voltage switching unit, and the gate of the seventh NMOS transistor is respectively connected to the gate and drain of the eighth NMOS transistor and one end of the second resistor, and A positive and negative voltage charge pump circuit characterized in that the other end of the second resistor is connected to the positive voltage output terminal of the positive voltage charge pump unit, and the sources of the eighth NMOS transistor and the seventh NMOS transistor, the other end of the third resistor and the fourth capacitor, and the sources of the sixth NMOS transistor and the fifth NMOS transistor are each grounded.
In Article 7, A positive and negative voltage charge pump circuit characterized in that the voltage conversion unit includes a hysteresis inverter, a logic level conversion sub-unit, and a switching sub-unit, wherein the input terminal of the hysteresis inverter is connected to the output terminal of the voltage sampling comparison unit, the output terminal of the hysteresis inverter is connected to the input terminal of the logic level conversion sub-unit, and the output terminal of the logic level conversion sub-unit is connected to the input terminal of the switching sub-unit.
In Article 8, The above logic level conversion sub-unit includes a 6th inverter, a 7th inverter, a 12th NMOS transistor, a 13th NMOS transistor, a 14th NMOS transistor, a 15th NMOS transistor, a 16th NMOS transistor, a 17th NMOS transistor, an 18th NMOS transistor, a 10th PMOS transistor, an 11th PMOS transistor, a 12th PMOS transistor, a 13th PMOS transistor, a 14th PMOS transistor, a 15th PMOS transistor, a 5th capacitor, a 6th capacitor, a 3rd NAND gate, a 4th NAND gate, an XOR gate, and a plurality of digital delay units, wherein the input terminal of the 6th inverter is connected to the output terminal of the hysteresis inverter, the output terminal of the 6th inverter is connected to the input terminal of the 7th inverter and the gate of the 13th NMOS transistor, the output terminal of the 7th inverter is connected to the input terminal of the switching sub-unit and the gate of the 14th NMOS transistor, and the X node is the output terminal of the hysteresis inverter and the of the 1st digital delay unit The input terminal and the input terminal of the XOR gate are respectively connected, and a plurality of digital delay units are serially connected between the output terminal of the first digital delay unit and the input terminal of the last digital delay unit, the output terminal of the last digital delay unit is connected to another input terminal of the XOR gate, and the output terminal of the XOR gate is respectively connected to the gates of the 18th NMOS transistor and the 17th NMOS transistor, and the gates of the 14th PMOS transistor and the 15th PMOS transistor, and the drain of the 15th PMOS transistor is connected to one end of the 6th capacitor and the drain of the 18th NMOS transistor, the source of the 18th NMOS transistor is connected to the drain of the 14th NMOS transistor, and the other end of the 6th capacitor is respectively connected to the source of the 15th NMOS transistor, the input terminal of the 3rd NAND gate, and the drain of the 10th PMOS transistor, and the drain of the 15th NMOS transistor is connected to the drain of the 16th NMOS transistor, and the The source of the 16th NMOS transistor is connected to the drain of the 11th PMOS transistor, one end of the 5th capacitor, and the input terminal of the 4th NAND gate, and the other end of the 5th capacitor is connected to the drain of the 14th PMOS transistor and the drain of the 17th NMOS transistor, respectively; the source of the 17th NMOS transistor is connected to the drain of the 13th NMOS transistor, and the gate of the 12th NMOS transistor is connected to the drain of the 5th NMOS transistor; the drain of the 12th NMOS transistor is connected to the drain and gate of the 13th PMOS transistor, and the gates of the 16th NMOS transistor and the 15th NMOS transistor, respectively; the source of the 13th PMOS transistor is connected to the drain and gate of the 12th PMOS transistor, and the gates of the 11th PMOS transistor and the 10th PMOS transistor, respectively; and the source of the 12th PMOS transistor, the 11th PMOS transistor, and the 10th PMOS transistor A positive and negative voltage charge pump circuit characterized in that the drains of the 15th NMOS transistor and the 16th NMOS transistor are all connected to the positive voltage output terminal of the positive voltage charge pump unit, the sources of the 14th NMOS transistor, the 13th NMOS transistor and the 12th NMOS transistor are each grounded, the sources of the 14th PMOS transistor and the 15th PMOS transistor are each connected to the negative rail voltage in the voltage domain where they are located, the other input terminal of the 3rd NAND gate is connected to the output terminal of the 4th NAND gate and the other input terminal of the switching sub-unit, and the output terminal of the 3rd NAND gate is connected to the other input terminal of the 4th NAND gate.
In Article 9, The switching sub-unit comprises a 16 PMOS transistor and a 17 PMOS transistor, wherein the gate of the 16 PMOS transistor is connected to the output terminal of the 4th NAND gate, the source of the 16 PMOS transistor is connected to the positive voltage output terminal of the positive voltage charge pump unit, the gate of the 17 PMOS transistor is connected to the output terminal of the 7th inverter, the source of the 17 PMOS transistor is connected to the power supply voltage, and the drains of the 17 PMOS transistor and the 16 PMOS transistor are used as the output terminals of the switching sub-unit, characterized by a positive and negative voltage charge pump circuit.
In Article 10, The positive and negative voltage charge pump circuit is characterized in that the negative voltage charge pump module includes a second clock conversion unit and a negative voltage charge pump unit, the input terminal of the second clock conversion unit is connected to the output terminal of the clock generation module, the output terminal of the second clock conversion unit is connected to the input terminal of the negative voltage charge pump unit, and the input terminal of the negative voltage charge pump unit is connected to the output terminal of the voltage conversion unit.
In Article 11, The above-mentioned second clock conversion unit includes an 8th inverter, a 9th inverter, a 10th inverter, an 11th inverter, a 12th inverter, a 5th NAND gate, and a 6th NAND gate, and The input terminal of the 8th inverter is connected to the output terminal of the clock generation module and the input terminal of the 6th NAND gate, the output terminal of the 8th inverter is connected to the input terminal of the 5th NAND gate, the output terminal of the 5th NAND gate is connected to the input terminal of the 9th inverter, the output terminal of the 9th inverter is connected to the 5th output terminal and the input terminal of the 10th inverter, the output terminal of the 10th inverter is connected to another input terminal and the 6th output terminal of the 6th NAND gate, the output terminal of the 6th NAND gate is connected to the input terminal of the 11th inverter, the output terminal of the 11th inverter is connected to the 8th output terminal and the input terminal of the 12th inverter, and the output terminal of the 12th inverter is connected to another input terminal and the 7th output terminal of the 5th NAND gate, characterized by an anode and cathode voltage charge pump circuit.
In Article 12, The above-described cathode voltage charge pump unit includes an 18th PMOS transistor, a 19th PMOS transistor, a 19th NMOS transistor, a 20th NMOS transistor, a 20th PMOS transistor, a 21st PMOS transistor, a 21st NMOS transistor, a 22nd NMOS transistor, a 7th capacitor, an 8th capacitor, and a 9th capacitor, and The gate of the 18th PMOS transistor is connected to the 8th output terminal of the 2nd clock conversion unit, and the drains of the 18th PMOS transistor and the 19th PMOS transistor are each connected to the output voltage of the voltage conversion unit, and the source of the 18th PMOS transistor is each connected to one end of the 8th capacitor and the source of the 19th NMOS transistor, respectively; the gate of the 19th NMOS transistor is connected to the 6th output terminal of the 2nd clock conversion unit, and the gate of the 19th PMOS transistor is connected to the 5th output terminal of the 2nd clock conversion unit, and the source of the 19th PMOS transistor is each connected to one end of the 7th capacitor and the source of the 20th NMOS transistor, respectively; the gate of the 20th NMOS transistor is connected to the 7th output terminal of the 2nd clock conversion unit, and the drains of the 19th NMOS transistor, the 20th NMOS transistor, the 20th PMOS transistor, and the 21st PMOS transistor are each grounded, and the 21st PMOS transistor A positive and negative voltage charge pump circuit characterized in that the gate is respectively connected to the source of the 20th PMOS transistor, the other end of the 7th capacitor, the gate of the 22nd NMOS transistor, and the source of the 21st NMOS transistor, and the gate of the 20th PMOS transistor is respectively connected to the source of the 21st PMOS transistor, the other end of the 8th capacitor, the gate of the 21st NMOS transistor, and the source of the 22nd NMOS transistor, and the drains of the 21st NMOS transistor and the 22nd NMOS transistor are respectively connected to one end of the 9th capacitor and the negative voltage output terminal, and the other end of the 9th capacitor is grounded.
An integrated circuit chip characterized by including a positive and negative voltage charge pump circuit according to any one of claims 1 to 13.
A communication terminal characterized by including an anode and a cathode voltage charge pump circuit according to any one of claims 1 to 13.

Description

Positive and negative voltage charge pump circuits, chips, and communication terminals The present invention belongs to the field of analog integrated circuit technology and relates to positive and negative voltage charge pump circuits, and simultaneously relates to an integrated circuit chip comprising said positive and negative voltage charge pump circuits and a corresponding communication terminal. As the integration density of integrated circuits increases, process nodes evolve to sub-micrometer depths, and the application environments of chips diversify, charge pump circuits are being widely applied as basic module circuits in various integrated circuit products. The primary function of a charge pump circuit is to better meet system design specifications by providing a positive voltage source higher than the positive rail of the input power supply and a negative voltage source lower than the negative rail of the input power supply. While positive power high-voltage charge pump circuits already exist in a relatively large number of applications, as system specifications continue to increase, an increasing number of electronic systems must be able to internally generate both positive and negative high voltages simultaneously for stable and reliable operation. Consequently, the demand for charge pump circuit designs capable of generating stable and reliable voltages that are higher than the positive rail of the input power supply and lower than the negative rail is becoming increasingly urgent. Chinese invention patent number ZL 200810142157.2 discloses a positive and negative voltage charge pump circuit that operates based on an asymmetric cross-linked cross-sectional cascade charge pump structure and implements a positive high voltage or a negative high voltage output through a selector. However, the circuit cannot simultaneously output positive and negative voltages. Additionally, invention patent number ZL 201610004368.4 discloses a charge pump circuit for generating positive and negative voltage sources that implements the output of positive and negative voltage sources by controlling capacitor charging and discharging with three clock signals implementing a fixed pulse sequence using a three-phase divider. Although the circuit can implement positive and negative voltage source outputs, it is very limited in practical applications because the absolute value of the output voltage source is lower than the input voltage source. FIG. 1 is a schematic block diagram of an anode and cathode voltage charge pump circuit provided in an embodiment of the present invention. FIG. 2 is a schematic diagram showing the circuit of the positive voltage charge pump module in the positive and negative voltage charge pump circuit provided in an embodiment of the present invention. FIG. 3 is a schematic diagram showing the circuit of a transient enhancement module in an anode and cathode voltage charge pump circuit provided in an embodiment of the present invention. FIG. 4 is a schematic diagram showing the circuit of a cathode voltage charge pump module in an anode and cathode voltage charge pump circuit provided in an embodiment of the present invention. Hereinafter, the technical details of the present invention will be explained in more detail by combining the drawings and specific embodiments. In order to simultaneously and stably and reliably output a voltage higher than the positive rail of the input power supply and lower than the negative rail of the input power supply, and to flexibly and quickly set the output negative voltage, as illustrated in FIG. 1, in one embodiment of the present invention, a positive and negative voltage charge pump circuit is provided, comprising a clock generation module (100), a positive voltage charge pump module (101), a transient enhancement module (102), and a negative voltage charge pump module (103). The output terminal of the clock generation module (100) is connected to the input terminals of the positive voltage charge pump module (101) and the negative voltage charge pump module (103), and the output terminal of the positive voltage charge pump module (101) is connected to the input terminal of the transient enhancement module (102). The output terminal of the transient enhancement module (102) is connected to the input power terminal of the negative voltage charge pump module (103), and the power terminals of the clock generation module (100), the positive voltage charge pump module (101), and the transient enhancement module (102) are all connected to the power supply voltage VDD. The positive voltage charge pump module (101) generates a positive voltage based on a clock signal output by the clock generation module (100), and the positive voltage and power supply voltage are sampled by the transient enhancement module (102) as input voltage sources, converted into current, and then compared. Based on the comparison result, a switchable input voltage is supplied to the nega