KR-102964756-B1 - vias to the rear power rail through the active area

Abstract

According to an embodiment of the present invention, a semiconductor device comprises a first source/drain and a second source/drain. A first source/drain contact comprises a first portion and a second portion. The first portion of the first source/drain contact is located immediately above the first source/drain. The second portion of the first source/drain contact extends vertically past the first source/drain. The first source/drain is in direct contact with three different faces of the first section of the second portion of the first source/drain contact.

Inventors

• 무케시, 사가리카
• 자인, 니킬
• 그랜트, 데비카
• 자이, 뤼룽
• 최, 기식
• 로이 차우두리, 프라부디아

Assignees

• 인터내셔널 비지네스 머신즈 코포레이션

Dates

Publication Date

20260513

Application Date

20230418

Priority Date

20220511

Claims (20)

1. In semiconductor devices, First source/drain and second source/drain of a semiconductor device; A first source/drain contact comprising a first part and a second part Includes, A semiconductor device wherein the first portion of the first source/drain contact is located directly atop the first source/drain, the bottom surface of the first portion of the first source/drain contact is in contact with the first source/drain, the second portion of the first source/drain contact extends vertically past the first source/drain, and the first source/drain is in direct contact with three different sides of the first section of the second portion of the first source/drain contact.
2. In paragraph 1, A semiconductor device further comprising an interlayer dielectric located around the first source/drain contact, wherein the interlayer dielectric contacts two side surfaces of the first portion of the first source/drain contact, and the interlayer dielectric contacts a plurality of side surfaces of the second portion of the first source/drain contact.
3. In paragraph 2, A semiconductor device further comprising a trench liner located around the first source/drain contact, wherein the trench liner contacts a second side surface of the first portion of the first source/drain contact, and the trench liner contacts a plurality of second sides of the second portion of the first source/drain contact.
4. In paragraph 3, A semiconductor device in which the first portion of the first source/drain contact contacts the first source/drain and the interlayer dielectric.
5. In semiconductor devices, A first source/drain and a second source/drain of a semiconductor device - the first source/drain is smaller than the second source/drain - ; A first source/drain contact comprising a first part and a second part Includes, A semiconductor device wherein the first portion of the first source/drain contact is located immediately above the first source/drain, the second portion of the first source/drain contact extends vertically past the first source/drain, and the first source/drain is in direct contact with three different faces of the first section of the second portion of the first source/drain contact.
6. In paragraph 5, A semiconductor device further comprising a second source/drain contact located immediately above the second source/drain.
7. In paragraph 1, A semiconductor device in which the first portion of the first source/drain contact and the second portion of the first source/drain contact are L-shaped.
8. In paragraph 6, The above first source/drain is a semiconductor device located in a seat of the L.
9. In paragraph 8, A semiconductor device further comprising a rear power rail located immediately above a buried oxide layer, wherein the upper surface of the second portion of the first source/drain contact contacts the lower surface of the rear power rail.
10. In paragraph 1, A semiconductor device in which a critical dimension of the second portion of the first source/drain contact is smaller than the critical dimension of the first portion of the first source/drain contact.
11. In paragraph 1, A semiconductor device in which the sidewalls of a second section of the second part of the first source/drain contact are in contact with a buried oxide layer.
12. In paragraph 1, A semiconductor device in which the sidewalls of the second section of the second part of the first source/drain contact are in contact with a bottom dielectric isolation layer.
13. In paragraph 1, A semiconductor device in which the first source/drain and the second source/drain are an n-type epitaxy.
14. In paragraph 1, A semiconductor device in which the first source/drain and the second source/drain are p-type epitaxy.
15. In semiconductor devices, First source/drain and second source/drain of a semiconductor device; A first source/drain contact comprising a first portion and a second portion - the first portion of the first source/drain contact is located immediately above the first source/drain, the lower surface of the first portion of the first source/drain contact is in contact with the first source/drain, and the second portion of the first source/drain contact extends vertically past the first source/drain, and the first source/drain is in direct contact with three different faces of the first section of the second portion of the first source/drain contact - ; and A rear power rail in contact with the surface of the second part of the first source/drain contact. A semiconductor device including
16. In paragraph 15, A semiconductor device further comprising an interlayer dielectric located around the first source/drain contact, wherein the interlayer dielectric contacts two sides of the first portion of the first source/drain contact, and the interlayer dielectric contacts a plurality of sides of the second portion of the first source/drain contact.
17. In Paragraph 16, A semiconductor device further comprising a trench liner positioned around the first source/drain contact, wherein the trench liner contacts a second side of the first portion of the first source/drain contact, and the trench liner contacts a plurality of second sides of the second portion of the first source/drain contact.
18. In semiconductor devices, A first source/drain and a second source/drain of a semiconductor device - the first source/drain is smaller than the second source/drain - ; A first source/drain contact comprising a first portion and a second portion - the first portion of the first source/drain contact is located immediately above the first source/drain, and the second portion of the first source/drain contact extends vertically past the first source/drain, and the first source/drain is in direct contact with three different faces of the first section of the second portion of the first source/drain contact - ; and A rear power rail in contact with the surface of the second part of the first source/drain contact. A semiconductor device including
19. In Paragraph 18, A semiconductor device further comprising a second source/drain contact located immediately above the second source/drain.
20. In paragraph 15, A semiconductor device in which the critical dimension of the second portion of the first source/drain contact is smaller than the critical dimension of the first portion of the first source/drain contact.

Description

vias to the rear power rail through the active area [0001] The present invention relates generally to the field of microelectronics, and more specifically to a semiconductor device structure and a method for forming a semiconductor device. [0002] Nanosheets (NS) are a leading device architecture for continuous CMOS scaling. However, nanosheet technology has revealed problems when scaling down. Specifically, as devices become smaller and closer together, interference problems arise. Furthermore, as devices become smaller and closer together, it becomes increasingly difficult to connect to a backside power network. [0005] These and other objects, features, and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention, which is read in conjunction with the accompanying drawings. The drawings are intended to make it clear to those skilled in the art that the present invention can be easily understood, along with specific details for carrying out the invention, and therefore various features of the drawings are not in scale. The drawings are as follows. [0006] FIG. 1 shows a top-down view of a plurality of nanodevices according to an embodiment of the present invention. [0007] FIGS. 2 to 4 respectively show cross-sections X1 , X2 , and Y of the plurality of nanodevices after nanosheet formation, dummy gate formation, gate spacer and internal spacer formation, source/drain formation, and interlayer dielectric deposition and CMP. [0008] FIGS. 5 to 7 respectively show cross-sections X1 , X2 , and Y of the plurality of nanodevices after the formation of a gate and a gate cut dielectric pillar according to an embodiment of the present invention. [0009] FIGS. 8 to 10 respectively show cross-sections X1 , X2 , and Y of the plurality of nanodevices after the formation of the first trench according to an embodiment of the present invention. [0010] FIGS. 11 to 13 respectively show cross-sections X1 , X2 , and Y of the plurality of nanodevices after the formation of a trench liner according to an embodiment of the present invention. [0011] FIG. 14 shows a top-down view of a plurality of nanodevices after the formation of a second trench according to an embodiment of the present invention. [0012] FIGS. 15 to 17 respectively show cross-sections X1 , X2 , and Y of the plurality of nanodevices after the formation of the second trench according to an embodiment of the present invention. [0013] FIGS. 18 to 20 respectively illustrate cross-sections X1 , X2 , and Y of the plurality of nanodevices after the formation of the third trench, fourth trench, fifth trench, and lithography layer according to an embodiment of the present invention. [0014] FIGS. 21 to 23 respectively illustrate cross-sections X1, X2, and Y of a plurality of nanodevices after the formation of a via (VBPR) for a rear power rail, a first source/drain contact, and a second source/drain contact according to an embodiment of the present invention. [0015] FIGS. 24 to 26 respectively illustrate cross-sections X1, X2 , and Y of the plurality of nanodevices after the formation of a back-end-of-line (BEOL) layer and bonding to a carrier wafer according to an embodiment of the present invention. [0016] FIGS. 27 to 29 respectively illustrate cross-sections X1 , X2 , and Y of the plurality of nanodevices after the carrier wafer is flipped and the substrate is removed, according to an embodiment of the present invention. [0017] FIGS. 30 to 32 respectively illustrate cross-sections X1 , X2 , and Y of the plurality of nanodevices after the formation of a back power rail (BPR) and a back power distribution network (BSPDN) according to an embodiment of the present invention. [0018] FIGS. 33 to 35 respectively illustrate cross-sections X1 , X2 , and Y of the plurality of nanodevices after the formation of a shallow trench device isolation (STI) region and a bottom dielectric isolation (BDI) layer according to an embodiment of the present invention. [0019] FIGS. 36 to 38 respectively illustrate cross-sections X1 , X2 , and Y of the plurality of nanodevices after the formation of the first trench according to an embodiment of the present invention. [0020] FIGS. 39 to 41 respectively illustrate cross-sections X1 , X2 , and Y of the plurality of nanodevices after the formation of the BEOL layer and bonding to the carrier wafer according to an embodiment of the present invention. [0021] FIGS. 42 to 44 respectively illustrate cross-sections X1 , X2 , and Y of the plurality of nanodevices after the removal of the substrate according to an embodiment of the present invention. [0022] FIG. 45 illustrates cross-sections of different regions of a plurality of nanodevices in which the device is built on silicon (Si) after the removal of the substrate, according to an embodiment of the present invention. [0023] FIGS. 46 to 48 respectively show cross-sections X1 , X2 , and Y of the plurality of nanodevice