KR-102964760-B1 - Majora or fermion quantum computing devices manufactured by ion implantation methods

Abstract

A quantum computing device is manufactured by forming a first resist pattern on a superconducting layer that defines a device region and a sensing region within the device region. The superconducting layer within the sensing region is removed, exposing a region of the underlying semiconductor layer outside the device region. The exposed region of the semiconductor layer is injected to form an isolation region surrounding the device region. Using an etching process following the injection step, a portion of the device region of the superconducting layer adjacent to the sensing region and the isolation region is exposed. A first metal layer is deposited within the sensing region to form a tunnel junction gate. The sensing region gate is formed by bonding the semiconductor layer to a second metal layer. A nanorod contact is formed using the second metal within a portion of the device region outside the sensing region.

Inventors

• 홈즈, 스티븐
• 사다나, 데벤드라
• 하트, 션
• 베델, 스티븐
• 리, 닝
• 구만, 패트릭

Assignees

• 인터내셔널 비지네스 머신즈 코포레이션

Dates

Publication Date

20260513

Application Date

20201110

Priority Date

20191111

Claims (20)

1. In a quantum computing device, the device is: A device region located on a superconducting layer above a semiconductor layer; A sensing region located within the above device region—the sensing region includes a portion of the device region that does not include a superconducting layer—; A tunnel junction gate comprising a first metal within the above-mentioned sensing area; A chemical potential gate comprising a dielectric and the first metal within a portion of the device region outside the sensing region; A sensing region gate comprising a second metal coupled to a semiconductor layer within the above-mentioned sensing region; and A nanorod contact comprising a second metal coupled to the superconductor layer within a portion of the device region outside the sensing region. Quantum computing device.
2. In claim 1, the device region comprises a first nanorod region, a second nanorod region parallel to the first nanorod region, and a sensing region connecting the first nanorod region and the second nanorod. Quantum computing device.
3. In paragraph 1 or 2, the device is: A buffer layer formed on the first surface of a substrate; A first protective layer formed on the above buffer layer; and A semiconductor layer further comprising formed on the first protective layer Quantum computing device.
4. In paragraph 3, the buffer layer comprises indium aluminum arsenide. Quantum computing device.
5. In paragraph 3, the first protective layer comprises indium gallium arsenide. Quantum computing device.
6. In claim 1 or 2, the superconducting layer comprises aluminum. Quantum computing device.
7. In paragraph 1 or 2, the device is: A second protective layer formed between the semiconductor layer and the superconductor layer further comprising Quantum computing device.
8. In paragraph 1 or 2, the device is: It further includes an isolation region surrounding the device region, wherein the isolation region includes a region in which the superconductor layer is removed and a semiconductor layer is injected. Quantum computing device.
9. In a computer implementation method for manufacturing a quantum computing device, the method comprises: A step of forming a first resist pattern on a superconducting layer that defines a device region and a sensing region within the device region; A step of removing a superconductor layer within the sensing region using an etching process—the etching process exposes a region of an underlying semiconductor layer outside the device region not protected by the first resist pattern—; A step of implanting an exposed region of the semiconductor layer—the implanting step forms an isolation region surrounding the device region—; A step of exposing a portion of the device region of the superconductor layer adjacent to the sensing region and the isolation region using an etching process following the injection step; A step of forming a tunnel joint gate by depositing a first metal layer within the detection area; A step of forming a sensing region gate by bonding the semiconductor layer to the second metal layer; and A step comprising forming a nanorod contact using a second metal within a portion of the device region outside the sensing region. Computer implementation method.
10. In claim 9, the device region comprises a first nanorod region, a second nanorod region parallel to the first nanorod region, and a sensing region connecting the first nanorod region and the second nanorod region. Computer implementation method.
11. In paragraph 9 or 10, the above method is: A step of forming a buffer layer on a first surface of a substrate; A step of forming a first protective layer on the buffer layer; A step of forming the semiconductor layer on the first protective layer; and A method comprising the step of forming the superconducting layer on the semiconductor layer. Computer implementation method.
12. In claim 11, the buffer layer comprises indium aluminum arsenic. Computer implementation method.
13. In claim 11, the first protective layer comprises indium gallium arsenide. Computer implementation method.
14. In claim 9 or 10, the superconducting layer comprises aluminum. Computer implementation method.
15. In paragraph 9 or 10, the above method is: The method further comprises the step of forming a second protective layer between the semiconductor layer and the superconductor layer. Computer implementation method.
16. In paragraph 9 or 10, the above method is: The method further comprises the step of removing the first resist pattern before depositing the first metal layer. Computer implementation method.
17. In paragraph 9 or 10, the above method is: The method further comprises the step of forming a chemical potential gate by depositing a dielectric layer and a first metal layer within a portion of a device region outside the sensing region. Computer implementation method.
18. In claim 9 or 10, the step of depositing the first metal layer is performed in areas defined by the second resist pattern. Computer implementation method.
19. In claim 17, the second metal layer is formed by depositing the second metal layer in regions defined by the third resist pattern, and the third resist pattern protects the tunnel junction gate and the chemical potential gate. Computer implementation method.
20. In a superconductor manufacturing system comprising a lithography component, the superconductor manufacturing system performs operations when operated on at least one die to manufacture a quantum computing device, and the operations are: A step of forming a first resist pattern on a superconducting layer that defines a device region and a sensing region within the device region; A step of removing a superconductor layer within the sensing region using an etching process—the etching process exposes a region of an underlying semiconductor layer outside the device region not protected by the first resist pattern—; A step of implanting an exposed region of the semiconductor layer—the implanting step forms an isolation region surrounding the device region—; A step of exposing a portion of the device region of the superconductor layer adjacent to the sensing region and the isolation region using an etching process following the injection step; A step of forming a tunnel joint gate by depositing a first metal layer within the detection area; A step of forming a sensing region gate by bonding the semiconductor layer to a second metal layer; and A step comprising forming a nanorod contact using a second metal within a portion of the device region outside the sensing region. Superconductor manufacturing system.

Description

Majora or fermion quantum computing devices manufactured by ion implantation methods [0001] The present invention generally relates to a superconducting device, a method for fabricating, and a system for fabricating superconducting quantum devices. In particular, the present invention relates to a device, method, and system for Majorana fermion quantum computing devices fabricated with ion implant methods. [0002] Below, the prefix "Q" in any word or phrase in the specification indicates that the word or phrase refers to the quantum computing context unless explicitly distinguished otherwise. [0003] Molecules and subatomic particles follow the laws of quantum mechanics, which is a branch of physics that explores how the physical world operates at its most fundamental levels. At these levels, particles behave in strange ways, taking on two or more states simultaneously and interacting with other particles that are very far away. Quantum computing uses these quantum phenomena to process information. [0022] Novel features considered to be features of the present invention are described in the appended claims. However, the present invention itself, as well as preferred modes of use, additional purposes, and advantages, will be best understood by referring to the following detailed description of exemplary embodiments and reading it together with the accompanying drawings. [0023] FIG. 1 illustrates a block diagram of a network of data processing systems in which exemplary embodiments can be implemented. [0024] FIG. 2 illustrates a Majorana fermion quantum computing device manufactured by ion implantation methods according to one exemplary embodiment. [0025] FIG. 3 illustrates a block diagram of an exemplary configuration achieved in the manufacture of a Majorana fermion quantum computing device according to one exemplary embodiment. [0026] FIG. 4 illustrates a block diagram of an exemplary configuration achieved in the manufacture of a Majorana fermion quantum computing device according to one exemplary embodiment. [0027] FIG. 5 illustrates a block diagram of an exemplary configuration achieved in the manufacture of a Majorana fermion quantum computing device according to one exemplary embodiment. [0028] FIG. 6 illustrates a block diagram of an exemplary configuration achieved in the manufacture of a Majorana fermion quantum computing device according to one exemplary embodiment. [0029] FIG. 7 illustrates a block diagram of an exemplary configuration achieved in the manufacture of a Majorana fermion quantum computing device according to one exemplary embodiment. [0030] FIG. 8 illustrates a block diagram of an exemplary configuration achieved in the manufacture of a Majorana fermion quantum computing device according to one exemplary embodiment. [0031] FIG. 9 illustrates a block diagram of an exemplary configuration achieved in the manufacture of a Majorana fermion quantum computing device according to one exemplary embodiment. [0032] FIG. 10 illustrates a block diagram of an exemplary configuration achieved in the manufacture of a Majorana fermion quantum computing device according to one exemplary embodiment. [0033] FIG. 11 illustrates a block diagram of an exemplary configuration achieved in the manufacture of a Majorana fermion quantum computing device according to one exemplary embodiment. [0034] FIG. 12 illustrates a block diagram of an exemplary configuration achieved in the manufacture of a Majorana fermion quantum computing device according to one exemplary embodiment. [0035] FIG. 13 illustrates a block diagram of an exemplary configuration achieved in the manufacture of a Majorana fermion quantum computing device according to one exemplary embodiment. [0036] FIG. 14 illustrates a block diagram of an exemplary configuration achieved in the manufacture of a Majorana fermion quantum computing device according to one exemplary embodiment. [0037] FIG. 15 illustrates a block diagram of an exemplary configuration achieved in the manufacture of a Majorana fermion quantum computing device according to one exemplary embodiment. [0038] FIG. 16 illustrates a block diagram of an exemplary configuration achieved in the manufacture of a Majorana fermion quantum computing device according to one exemplary embodiment. [0039] FIG. 17 illustrates a block diagram of an exemplary configuration achieved in the manufacture of a Majorana fermion quantum computing device according to one exemplary embodiment. [0040] FIG. 18 illustrates a block diagram of an exemplary configuration achieved in the manufacture of a Majorana fermion quantum computing device according to one exemplary embodiment. [0041] FIG. 19 illustrates a block diagram of an exemplary configuration achieved in the manufacture of a Majorana fermion quantum computing device according to one exemplary embodiment. [0042] FIG. 20 illustrates a block diagram of an exemplary configuration achieved in the manufacture of a Majorana fermion quantum computing device accordi