KR-102964836-B1 - ACTIVE MATRIX CIRCUIT FOR HIGH-SPEED DRIVING OF PHOTODIODE ARRAY WITH CHARGE INJECTION AND CLOCK FEEDTHROUGH NOISE COMPENSATION AND METHOD FOR OPERATING THE SAME

KR102964836B1KR 102964836 B1KR102964836 B1KR 102964836B1KR-102964836-B1

Abstract

An active matrix circuit for high-speed driving of a photodiode array capable of charge injection and clock feedthrough noise compensation and a driving method thereof are disclosed. An active matrix array for high-speed driving of a photodiode array capable of charge injection and clock feedthrough noise compensation according to one embodiment of the present invention may include: a first array cell that transmits the output of a first photodiode to a signal reading line based on a first control signal; a second array cell that disconnects from the signal reading line based on a second control signal inverted with respect to the first control signal; a first compensation circuit cell that has a connection structure mutually inverted with respect to the switch connection structure of the first array cell and operates based on a third control signal corresponding to the first control signal; and a second compensation circuit cell that has a connection structure mutually inverted with respect to the switch connection structure of the second array cell and operates based on a fourth control signal corresponding to the second control signal.

Inventors

지동우
오해찬

Assignees

아주대학교산학협력단

Dates

Publication Date: 20260513
Application Date: 20241205

Claims (15)

In an active matrix array for high-speed driving of a photodiode array capable of charge injection and clock feedthrough noise compensation, A first array cell that transmits the output of a first photodetector to a signal reading line based on a first control signal; A second array cell in which the connection with the signal reading line is released based on a second control signal inverted with respect to the first control signal; A first compensation circuit cell having a switch connection structure and a mutually inverted connection structure of the first array cell and operating based on a third control signal corresponding to the first control signal; and A second compensation circuit cell having a switch connection structure and a mutually inverted connection structure of the second array cell, and operating based on a fourth control signal corresponding to the second control signal, An active matrix array including
In paragraph 1, The above first array cell is, The apparatus includes a first photodiode that generates a photocurrent corresponding to incident light, a first switch that connects the output signal of the first photodiode to a signal reading line based on a first control signal, and a second switch for applying a preset bias voltage to the first photodiode based on the first control signal. The above second array cell is, An active matrix array comprising: a second photodetector that generates a photocurrent corresponding to incident light; a third switch that connects the output signal of the second photodetector to the signal reading line based on a second control signal which is a signal inverted with respect to the first control signal; and a fourth switch for applying a bias voltage to the second photodetector based on the second control signal.
In paragraph 2, The above-mentioned first compensation circuit cell is, A first compensation switch and a second compensation switch are respectively connected to the signal reading line and the bias voltage such that the connection method for the signal reading line and the bias voltage of the first switch and the second switch is mutually inverted, and The above second compensation circuit cell is, An active matrix array comprising a third compensation switch and a fourth compensation switch respectively connected to the signal reading line and the bias voltage such that the connection method for the signal reading line and the bias voltage of the third switch and the fourth switch is mutually inverted.
In paragraph 1, An active matrix array characterized in that a first charge moving to the signal reading line due to the operation of the first array cell and the second array cell, and a second charge moving to the signal reading line due to the operation of the first compensation circuit cell and the second compensation circuit cell, have the same magnitude and opposite polarity.
In paragraph 1, An active matrix array characterized in that the first array cell and the second array cell are placed in different rows in the active matrix array.
In paragraph 5, The first control signal is a first row unit control signal for selecting the first array cell in the active matrix array and connecting the first photodetector to the signal reading line, and An active matrix array characterized in that the second control signal is a second row unit control signal for releasing the connection with the signal reading line of the second array cell that was previously selected in the active matrix array.
In paragraph 3, The first switch is either an N-type transistor or a P-type transistor, and the second switch is the other one among the N-type transistor and the P-type transistor. The third switch is a transistor of the same type as the first switch, and the fourth switch is a transistor of the same type as the second switch, The first compensation switch and the third compensation switch are transistors of the opposite type to the first switch, and the second compensation switch and the fourth compensation switch are transistors of the opposite type to the second switch, wherein The first switch and the third switch are connected to the signal reading line, and the second switch and the fourth switch are connected to the bias voltage. An active matrix array characterized in that the first compensation switch and the third compensation switch are connected to the signal reading line, and the second compensation switch and the fourth compensation switch are connected to the bias voltage.
In paragraph 4, The first charge above includes a charge generated by the gate-drain parasitic capacitance, gate-source parasitic capacitance, and channel charge of a plurality of switch elements provided in the first array cell and the second array cell, and An active matrix array characterized in that the second charge comprises a charge generated by the gate-drain parasitic capacitance, gate-source parasitic capacitance, and channel charge of a plurality of switch elements provided in the first compensation circuit cell and the second compensation circuit cell.
In paragraph 1, The above active matrix array is, An active matrix array characterized by removing the charge generated when sequentially selecting the first array cell and the second array cell through the first compensation circuit cell and the second compensation circuit cell, thereby ensuring that only the photocurrent generated in the first photodetector is transmitted to the signal reading line.
In an active matrix circuit for high-speed driving of a photodiode array capable of charge injection and clock feedthrough noise compensation, Each having a photodetector that generates a photocurrent corresponding to incident light, a read switch that connects the output signal of the photodetector to a signal read line based on a control signal, and a bias switch for applying a preset bias voltage to the photodetector based on the control signal, and a plurality of array cells arranged to form a matrix having a plurality of rows and a plurality of columns; A compensation circuit cell having a switch arranged to have a connection structure mutually inverted with the connection method for the signal reading line of the reading switch and the bias switch and the bias voltage, so as to offset charge injection and clock feedthrough noise caused by the operation of the array cell selected by the control signal among the plurality of array cells and the previously selected array cell; A control module for applying the control signal to each of the plurality of rows of the plurality of array cells and the compensation circuit cells; A bias module for applying the bias voltage corresponding to each of the plurality of columns of the plurality of array cells and the compensation circuit cells; and A reading module for obtaining the output signal from each of the plurality of columns of the plurality of array cells and the compensation circuit cells, An active matrix circuit including
In Paragraph 10, An active matrix circuit characterized in that, based on the control signal, when the read switch of any one of the plurality of array cells is turned on, the bias switch of any one of the array cells is turned off, and the output signal is transmitted to the read module through the signal read line corresponding to any one of the array cells.
In Paragraph 10, The above-mentioned read switch is either an N-type transistor or a P-type transistor, and the above-mentioned bias switch is the other one among the N-type transistor and the P-type transistor, The switch of the above compensation circuit cell includes a pair of transistors corresponding to the opposite type to the above read switch and the above bias switch, respectively, An active matrix circuit characterized in that the above-mentioned read switch is connected to the above-mentioned signal read line, and the above-mentioned bias switch is connected to the above-mentioned bias voltage.
In Paragraph 10, An active matrix circuit characterized in that a first charge moving to the signal reading line due to the operation of the plurality of array cells and a second charge moving to the signal reading line due to the operation of the compensation circuit cell have the same magnitude and opposite polarity.
In Paragraph 13, The first charge above includes a charge generated by the gate-drain parasitic capacitance, gate-source parasitic capacitance, and channel charge of the switch elements provided in the plurality of array cells, and An active matrix circuit characterized in that the second charge comprises a charge generated by the gate-drain parasitic capacitance, gate-source parasitic capacitance, and channel charge of the switch elements provided in the compensation circuit cell.
In a high-speed driving method for a photodiode array capable of charge injection and clock feedthrough noise compensation according to claim 1, A step of selecting the first array cell based on the first control signal and transmitting the output of the first photodetector to the signal reading line; A step of releasing the connection between the second array cell and the signal reading line based on the second control signal; and A step of operating the first compensation circuit cell and the second compensation circuit cell based on the third control signal and the fourth control signal to offset charge injection and clock feedthrough noise generated by the operation of the first array cell and the second array cell, Includes, A high-speed driving method for a photodiode array, characterized in that the first compensation circuit cell and the second compensation circuit cell are each formed with a connection structure that is mutually inverted with the switch connection structure of the first array cell and the second array cell, thereby generating a charge that is equal in magnitude and opposite in polarity to the charge injection and clock feedthrough noise.

Description

Active Matrix Circuit for High-Speed Driving of Photodiode Array Capable of Charge Injection and Clock Feedthrough Noise Compensation and Method for Operating the Same The present invention relates to an active matrix circuit for high-speed driving of a photodiode array capable of charge injection and clock feedthrough noise compensation, and a driving method thereof. Photodiodes are photoelectric conversion devices that convert light energy into electrical signals and are widely used in the fields of optical imaging and optical communication. In this regard, FIG. 1a is a diagram showing an active matrix circuit structure for high-speed driving of a conventional photodiode array. Referring to FIG. 1a, a conventional active matrix circuit is composed of a first switch that connects the output of a photodiode to a column reader (Col Readout) by a row-unit control signal (Row Addressing), and a second switch that connects the bias voltage (Col Bias) of the photodiode to the photodiode by a row-unit control signal. The first switch and the second switch operate according to mutually complementary control signals, so when the first switch is not operated, the photodiode is always biased through the second switch, which has the advantage of not requiring a separate time to charge the photodiode. FIG. 1b is a conceptual diagram showing the signal transmission flow through an active matrix circuit for high-speed driving of a conventional photodiode array. Referring to FIG. 1b, in a conventional active matrix circuit, when a specific photodiode is selected, an output signal can be generated immediately without charging time, enabling high-speed operation of the active matrix. Meanwhile, Fig. 1c is a conceptual diagram modeling a row in a single column unit in a conventional active matrix circuit structure. Referring to Fig. 1c, C GDN , C GSN , C GDP , and C GSP are parasitic capacitors of the transistor to model the clock feedthrough, and Q N and Q P represent the charge generated when the transistor channel is created or destroyed. In addition, FIG. 1d is a conceptual diagram illustrating a situation in which, in a conventional active matrix circuit structure, one photodiode in a column unit is selected by a row unit control signal, and the previously selected photodiode is disconnected from the column unit reader. Referring to Fig. 1d, the P1 switch of the first row is turned on, and the clock feedthrough of -Q GSP (V RS1 x C GSP ) and -Q GDP (V RS1 x C GDP ) and the charge injection of -Q P are transferred to the column unit signal line (CR), and the N1 switch is turned off, and the clock feedthrough of -Q GSN (V RS1 x C GSN ) and the charge injection of -Q N /2 are transferred to the column unit signal line. The remaining clock feedthrough of -Q GDN (V RS1 x C GDN ) and the charge injection of -Q N /2 are transferred to the bias voltage of the photodiode (Col Bias). In the same principle, when the P2 switch is turned off, the clock feedthrough of +Q GSP (V RS2 x C GSP ) and the charge injection of +Q P /2 are transferred to the column unit signal line, and when the N2 switch is turned on, the clock feedthrough and charge injection from the N2 switch are transferred to the bias voltage. The amount of charge that eventually moves to the column unit signal line is -Q GDP -Q P /2 - Q GSN -Q N /2. This charge lowers the voltage of the column unit signal line from V CR to V CRL , and the photocurrent coming from the photodiode cannot be used until the column unit reader charges the voltage of the column unit signal line back to V CR . In addition, the longer the signal line, the longer it takes to charge the voltage of the signal line in columns due to the RC value of the signal line, which may cause difficulties in using the active matrix at high speed. The technology forming the background of the present invention is disclosed in Korean Published Patent Application No. 10-2022-0108608. Figure 1a is a diagram showing an active matrix circuit structure for high-speed driving of a conventional photodiode array. FIG. 1b is a conceptual diagram showing the signal transmission flow through an active matrix circuit for high-speed driving of a conventional photodiode array. Figure 1c is a conceptual diagram modeling one row in one column unit in a conventional active matrix circuit structure. Figure 1d is a conceptual diagram illustrating a situation in which, in a conventional active matrix circuit structure, one photodiode in a column unit is selected by a row unit control signal, and the previously selected photodiode is disconnected from the column unit reader. FIG. 2 is a diagram showing the structure of an active matrix circuit for high-speed driving of a photodiode array capable of charge injection and clock feedthrough noise compensation according to one embodiment of the present invention. FIG. 3 is a diagram showing the structure of a compensation circuit for removing charge injection and clock feedthrough noise i