KR-102965269-B1 - INTEGRATED CIRCUIT DEVICE AND ELECTRONIC SYSTEM HAVING THE SAME

KR102965269B1KR 102965269 B1KR102965269 B1KR 102965269B1KR-102965269-B1

Abstract

An integrated circuit device according to the technical concept of the present invention comprises: a semiconductor substrate having a cell region and a dummy region on the outer edge of the cell region; a plurality of gate electrodes and a plurality of insulating layers alternately stacked along a third direction perpendicular to the main surface and extending in a first direction and a second direction parallel to and intersecting the main surface of the semiconductor substrate in the cell region; a plurality of dummy mold layers and a plurality of dummy insulating layers alternately stacked along a third direction in the dummy region; a plurality of channel structures penetrating the plurality of gate electrodes and a plurality of insulating layers in the cell region; and a plurality of dummy structures penetrating the plurality of dummy mold layers and a plurality of dummy insulating layers in the dummy region, wherein the plurality of dummy mold layers are arranged at the same level as the plurality of gate electrodes in the third direction, and the plurality of dummy insulating layers are arranged at the same level as the plurality of insulating layers in the third direction, and the carbon concentration of the upper dummy mold layer in the plurality of dummy mold layers is smaller than the carbon concentration of the lower dummy mold layer.

Inventors

김지용
이정환
박환열

Assignees

삼성전자주식회사

Dates

Publication Date: 20260513
Application Date: 20210217

Claims (10)

A semiconductor substrate having a cell region and a dummy region on the outer edge of the cell region; In the cell region above, a plurality of gate electrodes and a plurality of insulating layers are alternately stacked along a third direction perpendicular to the main surface, extending in a first direction and a second direction parallel to and intersecting the main surface of the semiconductor substrate; In the above dummy region, a plurality of dummy mold layers and a plurality of dummy insulation layers alternately stacked along the third direction; In the cell region above, a plurality of channel structures penetrating the plurality of gate electrodes and the plurality of insulating layers; and In the above dummy region, a plurality of dummy structures penetrating the plurality of dummy mold layers and the plurality of dummy insulation layers; The plurality of dummy mold layers are disposed at the same level as the plurality of gate electrodes in the third direction, and The plurality of dummy insulation layers are arranged at the same level as the plurality of insulation layers in the third direction, and Among the plurality of dummy mold layers above, the carbon concentration of the upper dummy mold layer is smaller than the carbon concentration of the lower dummy mold layer. Integrated circuit device.
In paragraph 1, An integrated circuit device characterized in that the carbon concentration of the dummy mold layer of the upper layer is 0% to 80% of the carbon concentration of the dummy mold layer of the lower layer.
In paragraph 1, An integrated circuit device characterized in that, in the above dummy region, the carbon concentration is distributed in a sinusoidal form along the third direction from the main surface.
In paragraph 1, An integrated circuit device characterized by carbon and hydrogen being present as impurities at the interface between the gate electrode and the insulating layer.
In paragraph 1, An integrated circuit device characterized in that, within at least one selected dummy mold layer among the plurality of dummy mold layers, the carbon concentration of the upper interface and the lower interface, respectively, is greater than the carbon concentration of the central portion.
In paragraph 5, An integrated circuit device characterized in that the carbon concentration of the upper interface is greater than the carbon concentration of the lower interface.
In paragraph 5, An integrated circuit device characterized in that the carbon concentration of the upper interface is at least five times the carbon concentration of the central portion.
In paragraph 1, An integrated circuit element characterized in that the distance between adjacent plurality of channel structures is smaller than the distance between adjacent plurality of dummy structures.
In paragraph 1, The above plurality of gate electrodes are composed of a conductive first material, and An integrated circuit element characterized in that at least a portion of the sidewalls of the plurality of dummy mold layers are in contact with the first material.
In paragraph 1, The plurality of gate electrodes and the plurality of insulating layers form a gate stack, and An integrated circuit device characterized by further including a peripheral circuit structure disposed between the semiconductor substrate and the gate stack.

Description

Integrated circuit device and electronic system having the same The technical field of the present invention relates to an integrated circuit element and an electronic system including the same, and more specifically, to an integrated circuit element having a non-volatile vertical memory element and an electronic system including the same. To meet the requirements for superior performance and cost-effectiveness, it is necessary to increase the integration density of integrated circuit devices. In particular, the integration density of memory devices is a critical factor in determining the economic viability of a product. Since the integration density of two-dimensional memory devices is primarily determined by the area occupied by a unit memory cell, it is significantly influenced by the level of fine pattern formation technology. However, because fine pattern formation requires expensive equipment and the area of the chip die is limited, the integration density of two-dimensional memory devices remains limited despite increasing. Accordingly, vertical memory devices with a three-dimensional structure are required. FIG. 1 is a block diagram showing an integrated circuit element according to an embodiment of the technical concept of the present invention. FIG. 2 is an equivalent circuit diagram of a memory cell array of an integrated circuit element according to an embodiment of the technical concept of the present invention. FIG. 3 is a plan view showing the components of an integrated circuit element according to an embodiment of the technical concept of the present invention. FIG. 4 is a cross-sectional view taken along the line IV-IV' of FIG. 3, FIG. 5 is an enlarged view of part V of FIG. 4, FIG. 6 is an enlarged view of part VI of FIG. 4, and FIG. 7 is an enlarged view of part VII of FIG. 4. FIGS. 8 to 10 are cross-sectional views of an integrated circuit element according to another embodiment of the technical concept of the present invention. FIGS. 11 and FIGS. 12 are block diagrams illustrating a method for manufacturing an integrated circuit element according to an embodiment of the technical concept of the present invention. FIGS. 13a to 13e are cross-sectional views illustrating a method for manufacturing an integrated circuit element according to an embodiment of the technical concept of the present invention in the order of process. FIG. 14 is a drawing showing an electronic system including an integrated circuit element according to an embodiment of the technical concept of the present invention. FIG. 15 is a perspective view showing an electronic system including an integrated circuit element according to an embodiment of the technical concept of the present invention. FIGS. 16 and FIGS. 17 are cross-sectional views showing a semiconductor package including an integrated circuit element according to an embodiment of the technical concept of the present invention. Hereinafter, embodiments of the technical concept of the present invention will be described in detail with reference to the attached drawings. FIG. 1 is a block diagram showing an integrated circuit element according to an embodiment of the technical concept of the present invention. Referring to FIG. 1, the integrated circuit element (10) may include a memory cell array (20) and a peripheral circuit (30). The memory cell array (20) includes a plurality of memory cell blocks (BLK1, BLK2, …, BLKn). Each of the plurality of memory cell blocks (BLK1, BLK2, …, BLKn) may include a plurality of memory cells. The plurality of memory cell blocks (BLK1, BLK2, …, BLKn) may be connected to a peripheral circuit (30) through a bit line (BL), a word line (WL), a string select line (SSL), and a ground select line (GSL). The memory cell array (20) may be connected to a page buffer (34) via a bit line (BL) and to a row decoder (32) via a word line (WL), a string select line (SSL), and a ground select line (GSL). In the memory cell array (20), a plurality of memory cells included in a plurality of memory cell blocks (BLK1, BLK2, …, BLKn) may each be a flash memory cell. The memory cell array (20) may include a three-dimensional memory cell array. The three-dimensional memory cell array may include a plurality of NAND strings, and each of the plurality of NAND strings may include a plurality of memory cells connected to a plurality of vertically stacked word lines (WL). The peripheral circuit (30) may include a row decoder (32), a page buffer (34), a data input/output circuit (36), and control logic (38). Although not illustrated, the peripheral circuit (30) may further include various circuits such as a voltage generation circuit that generates various voltages required for the operation of the integrated circuit element (10), an error correction circuit for correcting errors in data read from the memory cell array (20), and an input/output interface. The above peripheral circuit (30) can receive an address (ADDR), a command (CMD), and a control sign