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KR-20260062102-A - CONNECTION PIN AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

KR20260062102AKR 20260062102 AKR20260062102 AKR 20260062102AKR-20260062102-A

Abstract

One embodiment provides a connection pin comprising a core portion including a copper alloy and a shell layer surrounding the outer surface of the core portion and having a thickness ranging from 3 μm to 10 μm, and having a resistance per unit length of 1 Ω/m or more and 20 Ω/m or less.

Inventors

  • 오희봉
  • 은동진
  • 김경태
  • 장현지
  • 이태현
  • 편민욱

Assignees

  • 덕산하이메탈(주)

Dates

Publication Date
20260507
Application Date
20241017

Claims (13)

  1. A core portion comprising a copper alloy (Cu alloy); and It includes a shell layer surrounding the outer surface of the core portion and having a thickness in the range of 3㎛ or more and 10㎛ or less, A connection pin having a resistance per unit length of 1 Ω/m or more and 20 Ω/m or less.
  2. In paragraph 1, A connecting pin, wherein the shell layer comprises at least one of copper (Cu), gold (Au), and silver (Ag).
  3. In paragraph 1, The above core portion extends in one direction and has a rod-shaped form having an aspect ratio of 1 or more and less than 4, and The diameter of the above core portion is 30㎛ or more and 400㎛ or less, and A connecting pin having a core portion having a length of 100㎛ or more and 1000㎛ or less.
  4. In paragraph 3, A connecting pin having a roughness (Ra) of both ends of the above-mentioned one direction ranging from 1 μm to 5 μm.
  5. In paragraph 1, A connecting pin having a tensile strength of 650 MPa or more and 1,000 MPa or less.
  6. In paragraph 1, A connection pin having a Vickers hardness of 140 Hv or more and 237 Hv or less.
  7. Substrate; A first conductive pad disposed on the above substrate; A second conductive pad disposed on the substrate spaced apart from the first conductive pad; A connecting pin disposed on the first conductive pad above; A first semiconductor chip disposed on the second conductive pad above; An interposer layer disposed on the first semiconductor chip and the connection pin; and A first solder plating layer disposed between the above-mentioned connection pin and the above-mentioned first conductive pad, comprising a first portion adjacent to the above-mentioned first conductive pad and a second portion adjacent to the above-mentioned connection pin, wherein the width of the first portion is the same as the width of the second portion. The above connection pin is, A core portion comprising a copper alloy (Cu alloy); and It includes a shell layer surrounding the outer surface of the core portion and having a thickness in the range of 3㎛ or more and 10㎛ or less, The above connection pin is a semiconductor package having a resistance per unit length of 1 Ω/m or more and 20 Ω/m or less.
  8. In Paragraph 7, A semiconductor package in which the shell layer comprises at least one of copper (Cu), gold (Au), and silver (Ag).
  9. In Paragraph 7, The above core portion extends in one direction and has a rod-shaped form having an aspect ratio of 1 or more and less than 4, and The diameter of the above core portion is 30㎛ or more and 400㎛ or less, and A semiconductor package having a core portion having a length of 100㎛ or more and 1000㎛ or less.
  10. In Paragraph 9, The above connection pin is a semiconductor package having a roughness (Ra) of both ends of the above one direction ranging from 1 μm to 5 μm.
  11. In Paragraph 7, The above connection pin is a semiconductor package having a tensile strength of 650 MPa or more and 1,000 MPa or less.
  12. In Paragraph 7, The above connection pin is a semiconductor package having a Vickers hardness of 140 Hv or more and 237 Hv or less.
  13. In Paragraph 7, A semiconductor package further comprising a second semiconductor chip disposed on top of the interposer layer.

Description

Connection pin and semiconductor package including the same The present invention relates to a connection pin comprising a shell layer and a semiconductor package comprising the same. With the miniaturization and increased performance of electronic products, there is a continuous demand for the miniaturization and lightweighting of electronic components mounted on such products. To meet these demands, semiconductor packages are evolving in a direction that enables miniaturization, multifunctionality, and high capacity. As one such method, stacked semiconductor packages have been proposed. A stacked semiconductor package is a package in which multiple individually assembled and electrically tested semiconductor packages are stacked vertically. Since a top semiconductor package is stacked on top of a bottom semiconductor package, it is also referred to as a package on package (PoP). As the pitch spacing of electrodes in stacked semiconductor packages decreases, the development of new concepts for connection materials is required. Accordingly, stable connections are being researched using fin-shaped connection materials, such as metal pins, conductive metal pins formed by plating a solder layer onto connection pins, or conductive connection pins. When using connection pins, the system can be operated without the risk of bridging even when the pitch spacing narrows; furthermore, since the connection pins are made of metals with high thermal conductivity, they can also provide a heat dissipation effect by releasing heat generated by the semiconductor to the substrate. Semiconductor connection pins are manufactured by cutting drawn copper wires. However, during this process, deformations such as roll-over and burr occur around the cut area where shear force is applied, resulting in an inconsistent shape of the connection pins. To solve this, there is a method of manufacturing connection pins using high-tensile copper alloy materials that exhibit strong resistance to deformation during cutting. However, when using high-tensile materials, there is a problem where fracture occurs during cutting and a dimple is formed on the cut surface, and depending on the alloy composition, electrical and thermal conductivity decrease rapidly compared to conventional copper materials. FIG. 1 is a cross-sectional view schematically showing a semiconductor package of one embodiment. FIG. 2 is an enlarged view of a portion of a semiconductor package of one embodiment. FIG. 3 is a perspective view schematically showing a connection pin of one embodiment. FIG. 4 is a cross-sectional view of a connecting pin according to one embodiment. Figures 5a and 5b are scanning electron microscope (SEM) images showing whether roll-over occurs on the connection pin. Figures 6a to 6d are 3D microscope images showing the results of evaluating the cross-sectional roughness of the connecting pin. Figure 7 is a schematic diagram illustrating a method for measuring the line resistance of a connection pin. Figure 8 is a schematic diagram illustrating a method for measuring the thermal conductivity of a connection pin. FIGS. 9a to 9e are electron microscope images of the end surfaces of the connecting pins according to the examples and comparative examples, respectively. The present invention is capable of various modifications and may take various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the invention to the specific disclosed forms, and it should be understood that the invention includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention. In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected," or "combined" with another component, it means that it may be directly placed/connected/combined with the other component, or that a third component may be placed between them. Meanwhile, in the present application, "direct placement" may mean that there are no additional layers, films, regions, plates, etc. added between a part such as a layer, film, region, or plate and another part. For example, "direct placement" may mean that two layers or two members are placed without using additional members such as adhesive members between them. Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of the components are exaggerated to effectively illustrate the technical content. "And/or" includes all one or more combinations that the associated configurations can define. Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component