KR-20260062103-A - IMAGE SENSOR PACKAGE

KR20260062103AKR 20260062103 AKR20260062103 AKR 20260062103AKR-20260062103-A

Abstract

One embodiment of the present invention comprises: a package substrate including a plurality of upper pads; an image sensor chip disposed on the package substrate and having a plurality of chip pads adjacent to at least some of the first to fourth sides, the chip pads having a first side and a second side facing in a first direction and a third and fourth side facing in a second direction perpendicular to the first direction; conductive wires electrically connecting the plurality of upper pads and at least some of the plurality of chip pads corresponding to each of the plurality of upper pads on the package substrate; a first reinforcing structure adjacent to the first side of the image sensor chip and spaced apart from the conductive wires; a dam disposed along the first to fourth sides of the image sensor chip and covering at least some of the plurality of chip pads and each of the conductive wires; a transparent cover disposed on the dam; and a sealant on the package substrate covering at least some of the image sensor chip, the dam and the transparent cover, and a first region adjacent to the first side where the first reinforcing structure is disposed. The image sensor package has the second to fourth regions adjacent to each of the second to fourth sides, wherein at least a portion of the conductive wires are disposed therein, and the volume ratio of the conductive wires to the dam in the first region is smaller than the volume ratio of the conductive wires to the dam in each of the second to fourth regions.

Inventors

김완선
한선우
이슬기
최윤석

Assignees

삼성전자주식회사

Dates

Publication Date: 20260507
Application Date: 20241017

Claims (10)

A package substrate including a plurality of upper pads; An image sensor chip disposed on the above-mentioned package substrate, having a first side and a second side facing in a first direction, and a third and a fourth side facing in a second direction perpendicular to the first direction, and comprising a plurality of chip pads adjacent to at least some of the first to fourth sides; Conductive wires electrically connecting at least a portion of the plurality of chip pads corresponding to each of the plurality of upper pads on the above package substrate; A first reinforcing structure adjacent to the first side of the image sensor chip and spaced apart from the conductive wires; A dam disposed along the first to fourth sides of the image sensor chip and covering at least a portion of each of the plurality of chip pads and the conductive wires; A transparent cover disposed on the above dam; and On the above package substrate, a sealant covering at least a portion of each of the image sensor chip, the dam, and the transparent cover is included, A first area adjacent to the first side and on which the first reinforcing structure is disposed; and Having the second to fourth regions adjacent to each of the second to fourth sides, wherein at least a portion of the conductive wires are disposed therein, An image sensor package in which the volume ratio of the conductive wires to the dam in the first region is smaller than the volume ratio of the conductive wires to the dam in each of the second to fourth regions.
In Article 1, The plurality of chip pads above include first chip pads adjacent to the first side, and The first reinforcing structure is an image sensor package spaced apart from the first chip pads in the first direction.
In Article 1, The first reinforcing structure is disposed on the upper surface of the image sensor chip, and The above dam is an image sensor package surrounding at least a portion of each of the upper surface and the side surface of the first reinforcing structure on the first region.
In Article 1, The first reinforcing structure is disposed on the upper surface of the package substrate, and The sealant is an image sensor package that surrounds at least a portion of each of the upper surface and the side surface of the first reinforcing structure on the first region.
In Article 1, The plurality of chip pads above include first chip pads adjacent to the first side, and An image sensor package in which at least some of the conductive wires electrically connect at least some of the plurality of upper pads and each of the first chip pads.
In Article 1, The above plurality of chip pads are image sensor packages not disposed on the first side.
In Article 1, At least a portion of the first reinforcing structure is an image sensor package in contact with the sealant.
In Article 1, It further includes a second reinforcing structure disposed adjacent to the second side of the image sensor chip, and The second reinforcing structure is an image sensor package having a second volume smaller than the first volume of the first reinforcing structure.
Package substrate; An image sensor chip disposed on the above-mentioned package substrate and having a first side and a second side, comprising a pixel array region in which active pixels are arranged and a pad region located outside the pixel array region in which a plurality of chip pads are disposed—the plurality of chip pads include first chip pads and second chip pads adjacent to each of the first side and the second side—; Conductive wires electrically connected to the second chip pads on the second side of the image sensor chip; A reinforcing structure disposed adjacent to the first chip pads on the first side of the image sensor chip; A dam disposed on at least a portion of the pad area of the image sensor chip and covering at least a portion of each of the first chip pads and the second chip pads; A transparent cover disposed on the above dam; and On the above package substrate, a sealant covering at least a portion of the sides of the image sensor chip and the dam, respectively, is included. The above image sensor chip is, A micro-lens layer disposed on the active pixels in the pixel array region; A first protective layer having an opening that exposes the first chip pads and the second chip pads on the pad area; and It includes a second protective layer covering each of the above-mentioned micro-lens layer and the above-mentioned first protective layer, and The above dam fills the opening that exposes the upper surface of each of the first chip pads and the second chip pads, and The reinforcing structure is disposed adjacent to the first chip pads on the upper surface of the second protective layer, and The above conductive wires are an image sensor package that electrically connects the second chip pads to the package substrate.
A package substrate including a plurality of upper pads; An image sensor chip disposed on the above-mentioned package substrate and having first to fourth sides, comprising inactive chip pads adjacent to the first side and active chip pads adjacent to each of the second to fourth sides; Conductive wires electrically connecting the plurality of upper pads of the package substrate and the active chip pads of the image sensor chip at each of the second to fourth sides of the image sensor chip; A reinforcing structure disposed on the first side of the image sensor chip; A dam disposed along the first to fourth sides of the image sensor chip and covering at least a portion of each of the inactive chip pads, the active chip pads, the reinforcing structure, and the conductive wire; A transparent cover disposed on the dam and spaced apart from the upper surface of the image sensor chip; and On the above package substrate, a sealant covering at least a portion of each of the image sensor chip, the dam, and the transparent cover is included, The reinforcing structure comprises a body portion, a lower adhesive film in contact with the upper surface of the image sensor chip below the body portion, and an upper adhesive film in contact with the lower surface of the transparent cover on the body portion. The above dam is an image sensor package surrounding the sides of the body portion, the lower adhesive film, and the upper adhesive film, respectively.

Description

Image Sensor Package The present invention relates to an image sensor package. An image sensor is a semiconductor-based sensor that receives light and generates an electrical signal, and may include a pixel array having a plurality of pixels and a logic circuit for driving the pixel array and generating an image. Each of the pixels may include a photodiode and a pixel circuit that converts an electric charge generated by the photodiode into an electrical signal. FIG. 1a is a plan view illustrating an image sensor package according to one embodiment of the present invention, and FIG. 1b is a cross-sectional view illustrating a cross-section along line I-I' of FIG. 1a. FIG. 2a is a partial enlarged view illustrating an area corresponding to region 'A' of FIG. 1b in an image sensor package according to one embodiment of the present invention, and FIG. 2b is a partial enlarged view illustrating areas corresponding to regions 'B' and 'C' of FIG. 1b in an image sensor package according to one embodiment of the present invention. FIG. 3a is a plan view illustrating an image sensor package according to one embodiment of the present invention, and FIG. 3b is a cross-sectional view illustrating a cross-sectional plane along the line II-II' of FIG. 3a. FIG. 4 is a plan view illustrating an image sensor package according to one embodiment of the present invention. FIG. 5 is a plan view illustrating an image sensor package according to one embodiment of the present invention. FIG. 6a is a plan view illustrating an image sensor package according to one embodiment of the present invention, and FIG. 6b is a cross-sectional view illustrating a cross-section along the line III-III' of FIG. 6a. FIG. 7a is a plan view illustrating an image sensor package according to one embodiment of the present invention, and FIG. 7b is a cross-sectional view illustrating a cross-sectional plane along the line IV-IV' of FIG. 7a. Figure 8a is a simulation graph comparing the stress values accumulated in the sensor chip according to the number of bonding wires placed, and Figure 8b is a simulation graph comparing the stress values accumulated in the sensor chip according to the location where the reinforcing structure is placed. FIGS. 9a to 9f are cross-sectional views schematically illustrating the manufacturing process of an image sensor package according to one embodiment of the present invention. Hereinafter, preferred embodiments of the present invention are described as follows with reference to the attached drawings. Unless otherwise specifically stated, terms such as 'upper,' 'upper surface,' 'lower,' 'lower surface,' and 'side surface' in this specification are based on the drawings and may actually vary depending on the direction in which the components are arranged. FIG. 1a is a plan view illustrating an image sensor package according to one embodiment of the present invention, and FIG. 1b is a cross-sectional view illustrating a cross-section along line I-I' of FIG. 1a. FIG. 2a is a partial enlarged view illustrating an area corresponding to region 'A' of FIG. 1b in an image sensor package (100) according to an embodiment of the present invention, and FIG. 2b is a partial enlarged view illustrating areas corresponding to regions 'B' and 'C' of FIG. 1b in an image sensor package (100) according to an embodiment of the present invention. FIG. 2a is a partial enlarged view illustrating a pixel array area (PA) and a light-blocking area (OB) of an image sensor chip (200), and FIG. 2b corresponds to partial enlarged views illustrating a pad area (PR) of an image sensor chip (200). Referring to FIGS. 1a to 2b, an image sensor package (100) of one embodiment may include a package substrate (110), an image sensor chip (200), a conductive wire (WB), a reinforcing structure (300), a dam (400), a transparent cover (500), a sealant (600), and external connection terminals (700). The package substrate (110) may include a substrate body (111), an upper pad (115), a lower pad (118), and upper and lower passivation layers (112a, 112b). For example, the substrate body (111) may include silicon, ceramic, organic material, glass, epoxy resin, etc. In some embodiments, the package substrate (110) may be a printed circuit board (PCB). The substrate body (111) may include single-layer or multi-layer wiring. The wiring may electrically connect the upper pad (115) and the lower pad (118). The image sensor chip (200) may be disposed on a package substrate (110) and may be mounted on the package substrate (110) in a wire bonding structure. The image sensor chip (200) may have a square or rectangular shape on a plane and may have a first side (S1) and a second side (S2) facing in a first direction (e.g., X-axis direction), and a third side (S3) and a fourth side (S4) facing in a second direction (e.g., Y-axis direction) intersecting the first direction. The image sensor chip (200) may include a plurality of chip pads (230), and the plurality of chip pads (230