KR-20260062118-A - ELECTRONIC DEVICE

Abstract

An electronic device comprises a substrate; insulating layers disposed on the substrate; signal lines disposed between the insulating layers; transistors connected to the signal lines; and light-emitting elements connected to the transistors, wherein the signal lines include a sequentially arranged second initialization line, a bias line, a bias scan line, a light-emitting line, a compensation scan line, an initialization scan line, a write scan line, a first initialization line, and a data line, and in a planar arrangement, a driving transistor among the transistors is disposed between the compensation scan line and the initialization scan line.

Inventors

• 방정석
• 김태현
• 유동일
• 임명훈

Assignees

• 삼성디스플레이 주식회사

Dates

Publication Date

20260507

Application Date

20241025

Claims (20)

1. Substrate; Insulating layers disposed on the above substrate; Signal lines disposed between the above insulating layers; Transistors connected to the above signal lines; It includes a light-emitting element connected to the above transistors, The above signal lines are, Each includes a second initialization line, a bias line, a bias scan line, a light emission line, a compensation scan line, an initialization scan line, a write scan line, a first initialization line, and a data line extended along the second direction, each of which is extended along the first direction and sequentially arranged along the second direction intersecting the first direction. In a planar view, the driving transistor among the transistors is a display panel positioned between the compensation scan line and the initialization scan line.
2. In Article 1, Among the above transistors, the compensation transistor connected to the compensation scan line and the first initialization transistor connected to the initialization scan line are a display panel spaced apart along the second direction with the driving transistor in between.
3. In Article 2, A display panel in which the semiconductor layer included in the compensation transistor and the first initialization transistor among the above transistors comprises a metal oxide, and the semiconductor layer included in the remaining transistors comprises polysilicon.
4. In Paragraph 3, The semiconductor layers including the metal oxide and the semiconductor layers including the polysilicon are arranged on a display panel on another layer.
5. In Paragraph 4, It further includes a gate pattern connecting the driving transistor and the compensation transistor, The above gate pattern is a display panel placed on the same layer as the above second initialization line.
6. In Article 5, The gate pattern above is a display panel that does not overlap with the initialization scan line, the compensation scan line, and the write scan line.
7. In Article 5, A display panel in which the gate pattern is non-overlapping with the initialization scan line and the write scan line, and a portion of the gate pattern intersects the compensation scan line.
8. In Article 5, The above insulating layers include sequentially stacked buffer layers and first to seventh insulating layers, and A first conductive layer disposed on the buffer layer and covered by the first insulating layer; A second conductive layer disposed on the first insulating layer and covered by the second insulating layer; A third conductive layer disposed on the second insulating layer and covered by the third insulating layer; A fourth conductive layer disposed on the third insulating layer and covered by the fourth insulating layer; A fifth conductive layer disposed on the fourth insulating layer and covered by the fifth insulating layer; A sixth conductive layer disposed on the fifth insulating layer and covered by the sixth insulating layer; and A display panel comprising a seventh conductive layer disposed on the sixth insulating layer and covered by the seventh insulating layer.
9. In Article 8, The semiconductor layers including the above polysilicon are a display panel included in the first conductive layer.
10. In Article 9, The gate electrode included in the above bias scan line, the above light-emitting line, the above write scan line, and the above driving transistor is a display panel included in the above second conductive layer.
11. In Article 10, Each of the above compensation injection line and the above initialization injection line includes a lower layer and an upper layer, and The lower layer of the compensation scan line, the lower layer of the initialization scan line, and the dummy electrode included in the driving transistor and overlapping with the gate electrode are included in the third conductive layer, and The above dummy electrode is a display panel with a defined opening that exposes the gate electrode.
12. In Article 11, The semiconductor layers containing the metal oxides are a display panel included in the fourth conductive layer.
13. In Article 12, The above bias line, the upper layer of the above compensation scan line, the upper layer of the above initialization scan line, and the first initialization line are a display panel included in the fifth conductive layer.
14. In Article 13, The above second initialization line and the above gate pattern are a display panel included in the above sixth conductive layer.
15. In Article 14, The above data line is a display panel included in the above seventh conductive layer.
16. In Article 15, It further includes a first power line that provides a first power voltage to the driving transistor, and A display panel comprising a first power line, a lower line included in the sixth conductive layer and extended along the first direction, and an upper line included in the seventh conductive layer and extended along the second direction, connected to the lower line through a contact hole defined in the sixth insulating layer.
17. In Article 16, The above lower line is a display panel connected to the dummy electrode through a contact hole penetrating the third to fifth insulating layers.
18. In Article 14, A display panel in which one end of the gate pattern overlaps with the opening and is connected to the gate electrode included in the driving transistor through a first contact hole penetrating the second to fifth insulating layers, and the other end of the gate pattern is connected to the semiconductor layer including the metal oxide through a second contact hole penetrating the fourth and fifth insulating layers.
19. In Article 14, A display panel comprising a first sub-line included in the sixth conductive layer and extended in the first direction, and a second sub-line included in the seventh conductive layer and connected to the first sub-line through a contact hole defined in the sixth insulating layer and extended in the second direction, wherein the second sub-line is connected to the data line.
20. In Article 1, The light-emitting element comprises a first electrode connected to the driving transistor, a second electrode disposed on the first electrode, and a light-emitting layer disposed between the first electrode and the second electrode, forming a display panel.

Description

ELECTRONIC DEVICE The present invention relates to an electronic device, and more specifically, to an electronic device with improved display quality. Generally, electronic devices that provide video to users, such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions, include electronic devices for displaying video. The electronic device generates video and provides the generated video to the user through a display screen. The electronic device includes a plurality of pixels for generating an image and a plurality of lines connected to the pixels. The pixels are driven by receiving driving signals through the lines. FIG. 1 is a perspective view of an electronic device according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an exemplary cross-section of the electronic device shown in FIG. 1. FIG. 3 is a drawing exemplarily illustrating a cross-section of the display panel shown in FIG. 2. Figure 4 is a block diagram of the electronic device shown in Figure 1. Figure 5 is a diagram illustrating the equivalent circuit of any one of the pixels shown in Figure 4. FIG. 6 is a timing diagram of scanning signals and light emission signals to explain the operation of the pixel illustrated in FIG. 5. FIG. 7 is a diagram exemplarily illustrating cross-sections of the light-emitting element, the first transistor, the fourth transistor, and the sixth transistor of the pixel illustrated in FIG. 5. FIG. 8 is a plan view illustrating the stacking relationship of conductive layers included in a pixel circuit according to one embodiment of the present invention. FIGS. 9a to 9g are plan views illustrating conductive patterns included in a conductive layer of a pixel circuit according to one embodiment of the present invention. FIG. 10 is a plan view illustrating conductive patterns included in a conductive layer of a pixel circuit according to one embodiment of the present invention. FIGS. 11 to 14 are plan views briefly illustrating the arrangement relationship of signal lines included in a pixel circuit according to one embodiment of the present invention. In this specification, where a component (or region, layer, part, etc.) is described as being “on,” “connected,” or “joined” another component, it means that it may be directly placed/connected/joined on the other component, or that a third component may be placed between them. Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the effective illustration of the technical content. “And/or” includes all one or more combinations that the associated components may define. Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise. Additionally, terms such as “below,” “lower,” “above,” and “upper” are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings. Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof. Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein. Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a perspective view of an electronic device according to an embodiment of the present invention. Referring to FIG. 1, an electronic device (DD) according to an embodiment of the present invention may have long sides extending parallel to a first direction (DR1) and short sides extending parallel to a second direction (DR2) intersecting the first direction (DR1). The corners of the electronic device (DD) connecting the long sides and the short sides may have a curved shape. The corners of the electronic device