KR-20260062170-A - SEMICONDUCTOR PACKAGE

KR20260062170AKR 20260062170 AKR20260062170 AKR 20260062170AKR-20260062170-A

Abstract

A semiconductor package according to an embodiment of the present invention comprises: a base structure including a base substrate, upper connection pads disposed on an upper surface of the base substrate, and an upper bonding insulating layer covering the upper surface of the base substrate and surrounding the sides of the upper connection pads; a semiconductor chip stack including a plurality of semiconductor chips that are stacked vertically on the base structure and electrically connected to the base structure, and have lower pads located on a lower surface, upper pads disposed on an upper surface, and through electrodes electrically connecting the lower pads and the upper pads, wherein the plurality of semiconductor chips include a lower semiconductor chip, and the lower pads of the lower semiconductor chip are in contact with the upper connection pads; a dummy chip disposed on the semiconductor chip stack; a bonding film disposed between the dummy chip and the semiconductor chip stack; and a plurality of bonding patterns disposed spaced apart from the plurality of semiconductor chips on the base structure. and a sealant covering at least a portion of each of the semiconductor chip stack, the dummy chip, the bonding film, and the plurality of bonding patterns on the base structure, wherein the lower pads of each of the semiconductor chips stacked on the lowest semiconductor chip among the plurality of semiconductor chips contact the upper pads of another semiconductor chip disposed therebelow.

Inventors

성하섭
정다운

Assignees

삼성전자주식회사

Dates

Publication Date: 20260507
Application Date: 20241025

Claims (10)

A base structure comprising a base substrate, upper connection pads disposed on the upper surface of the base substrate, and an upper bonding insulating layer covering the upper surface of the base substrate and surrounding the sides of the upper connection pads; A semiconductor chip stack comprising a plurality of semiconductor chips that are vertically stacked on the base structure and electrically connected to the base structure, and have lower pads located on the lower surface, upper pads disposed on the upper surface, and through electrodes electrically connecting the lower pads and the upper pads - the plurality of semiconductor chips includes a lower semiconductor chip, and the lower pads of the lower semiconductor chip are in contact with the upper connecting pads - ; A dummy chip placed on the above semiconductor chip stack; A bonding film disposed between the above dummy chip and the above semiconductor chip stack; A plurality of bonding patterns spaced apart from the plurality of semiconductor chips on the base structure; and The base structure comprises a semiconductor chip stack, a dummy chip, a bonding film, and a sealant covering at least a portion of each of the plurality of bonding patterns. A semiconductor package in which the lower pads of each of the semiconductor chips stacked on the lowest semiconductor chip among the plurality of semiconductor chips above contact the upper pads of another semiconductor chip disposed below it.
In paragraph 1, A semiconductor package in which the planar area of the above dummy chip is larger than the planar area of each of the above plurality of semiconductor chips.
In paragraph 1, A semiconductor package spaced apart from the base substrate, wherein the plurality of bonding patterns are disposed on the upper bonding insulating layer.
In paragraph 1, The above plurality of bonding patterns are semiconductor packages including a polymer.
In paragraph 1, The above dummy chip is spaced apart from the semiconductor chip stack by the bonding film, and The above dummy chip is a semiconductor package electrically isolated from the plurality of semiconductor chips.
In paragraph 1, A semiconductor package in which the level difference between the upper surface of the uppermost semiconductor chip among the plurality of semiconductor chips and the lower surface of the bonding film is greater than the level difference between the upper surface of the uppermost semiconductor chip and the upper surface of the bonding film.
A base structure comprising a base substrate and upper connection pads disposed on the upper surface of the base substrate; A semiconductor chip stack comprising a plurality of semiconductor chips stacked vertically on the base structure; A bonding pattern disposed spaced apart from the semiconductor chip stack on the base structure; A bonding film covering the upper part of the semiconductor chip stack; and It includes a dummy chip disposed on the bonding film above, and The above plurality of semiconductor chips are, A first semiconductor chip located at the bottom of the semiconductor chip stack and comprising first lower pads disposed on the bottom surface, first upper pads disposed on the top surface, and first through electrodes electrically connecting the first lower pads and the first upper pads; and It includes a second semiconductor chip located at the uppermost part of the semiconductor chip stack and comprising second lower pads disposed on the lower surface, and The first lower pads above are in contact with the upper connecting pads, and The bonding film protrudes further in the horizontal direction than each of the dummy chip and the plurality of semiconductor chips, and The above bonding film is a semiconductor package that covers at least a portion of the side of the second semiconductor chip.
In Paragraph 7, A semiconductor package in which, in the above vertical direction, the bonding pattern includes an area that overlaps with the bonding film.
In Paragraph 7, A semiconductor package in which the area of the bonding film covering the side of the dummy chip is smaller than the area of the bonding film covering the side of the second semiconductor chip, or the bonding film does not cover the side of the dummy chip.
A base structure comprising a base substrate, upper connection pads disposed on the upper surface of the base substrate, and an upper bonding insulating layer surrounding the side of each of the upper connection pads on the upper surface of the base substrate; A semiconductor chip stack disposed on the base structure and electrically connected to the upper connection pads—the semiconductor chip stack includes a bottom semiconductor chip located at the lowest level—; Bonding patterns spaced apart from the semiconductor chip stack on the upper bonding insulating layer; and A sealant covering the semiconductor chip stack and the bonding patterns on the upper surface of the base substrate, and The lowermost semiconductor chip comprises lower pads disposed on the lower surface and a lower insulating layer surrounding the sides of the lower pads. The above lower pads are in contact with the above upper connecting pads, and The above lower insulating layer is a semiconductor package in contact with the above upper bonding insulating layer.

Description

Semiconductor Package {SEMICONDUCTOR PACKAGE} The present invention relates to a semiconductor package. In response to the advancement of the electronics industry and user demands, electronic devices are becoming increasingly smaller and lighter. Consequently, semiconductor packages used in these devices are required to possess high performance and high capacity alongside these miniaturization and lightweighting requirements. To achieve high performance and high capacity alongside miniaturization and lightweighting, research and development are continuously being conducted on semiconductor chips containing through-hole electrodes and on semiconductor packages in which such chips are stacked. FIG. 1 is a schematic cross-sectional view illustrating a semiconductor package according to exemplary embodiments. FIG. 2 is a schematic plan view illustrating a semiconductor package according to exemplary embodiments. FIG. 3 is a schematic partial enlarged view illustrating a semiconductor package according to exemplary embodiments. FIGS. 4a to 4c are schematic partial enlarged views illustrating semiconductor packages according to exemplary embodiments. FIGS. 5 and 6 are schematic cross-sectional views illustrating semiconductor packages according to exemplary embodiments. FIGS. 7 to 12 are schematic plan views illustrating semiconductor packages according to exemplary embodiments. FIG. 13a is a schematic plan view illustrating a semiconductor package according to exemplary embodiments. FIG. 13b is a schematic plan view illustrating a semiconductor package according to exemplary embodiments. FIGS. 14, FIGS. 15, FIGS. 16a, FIGS. 17a, and FIGS. 18 are cross-sectional views illustrated in the order of process to explain a method for manufacturing a semiconductor package according to exemplary embodiments. FIGS. 16b and FIGS. 17b are partial enlarged views illustrated in the process sequence to explain a method for manufacturing a semiconductor package according to exemplary embodiments. Hereinafter, preferred embodiments of the present invention will be described as follows with reference to the attached drawings. In the following, terms such as 'top', 'upper part', 'upper surface', 'lower part', 'lower part', 'lower surface', 'side surface', etc., may be understood as referring to the drawings unless otherwise specified. FIG. 1 is a schematic cross-sectional view illustrating a semiconductor package according to exemplary embodiments. FIG. 2 is a schematic plan view illustrating a semiconductor package according to exemplary embodiments. FIG. 2 schematically illustrates a cross-sectional view of the semiconductor package of FIG. 1 cut along the cutting line I-I'. FIG. 3 is a schematic partial enlarged view illustrating a semiconductor package according to exemplary embodiments. FIG. 3 illustrates an enlarged view of region 'A' of FIG. 1. Referring to FIGS. 1 to 3, a semiconductor package (10) may include a base structure (100), bonding patterns (200), a semiconductor chip stack (300) comprising a plurality of semiconductor chips (300a, 300b, 300c), a bonding film (410), a dummy chip (420), and a sealing material (500). The base structure (100) may be, for example, a buffer chip comprising a plurality of logic elements and/or memory elements in a base element layer (120). Accordingly, the base structure (100) can transmit signals from a plurality of semiconductor chips (300a, 300b, 300c) stacked on top to the outside, and also transmit signals and power from the outside to the plurality of semiconductor chips (300a, 300b, 300c). The base structure (100) may perform logic and memory functions together through logic elements and memory elements, but according to an embodiment, the base structure (100) may include only logic elements to perform only logic functions. The base structure (100) may include a base substrate (110), a base element layer (120), a connection via (130), upper connection pads (151), an upper bonding insulating layer (155), lower connection pads (160), and connection conductors (170). The base substrate (110) may include, for example, a semiconductor element such as silicon or germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The base substrate (110) may have a Silicon On Insulator (SOI) structure. The base substrate (110) may include a conductive region, for example, an impurity-doped well, or an impurity-doped structure. The base substrate (110) may include various device isolation structures such as a Shallow Trench Isolation (STI) structure. The base substrate (110) may include an insulating layer in contact with upper connection pads (151) and an upper bonding insulating layer (155) on its upper surface. In this specification, the horizontal direction may be defined as a direction parallel to the upper surface of the base substrate (110), and the vertical direction may be defined as a direction p