Search

KR-20260062247-A - SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

KR20260062247AKR 20260062247 AKR20260062247 AKR 20260062247AKR-20260062247-A

Abstract

A semiconductor package according to the concept of the present invention comprises: a first semiconductor chip and a second semiconductor chip stacked in sequence; a first bump structure disposed between the first and second semiconductor chips and connecting them; a first bump protective film extending in a first direction between the first and second semiconductor chips and covering the sidewall of the first bump structure; and a first adhesive film interposed between the first bump protective film and the first semiconductor chip, wherein the first semiconductor chip includes a first upper conductive pad having a first edge inserted into the first bump structure, and the first adhesive film extends to cover the sidewall of the first upper conductive pad that is not inserted into the first bump structure, and the first thickness of the first upper conductive pad is greater than the second thickness of the first adhesive film.

Inventors

  • 정현수
  • 김혜진
  • 마금희

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260507
Application Date
20241028

Claims (10)

  1. A first semiconductor chip and a second semiconductor chip stacked in sequence; A first bump structure disposed between the first and second semiconductor chips and connecting them; A first bump protective film extending in a first direction between the first and second semiconductor chips and covering the side of the first bump structure; and A first adhesive film interposed between the first bump protective film and the first semiconductor chip, comprising: The first semiconductor chip includes a first upper conductive pad having a first edge that is inserted into the first bump structure, and The first adhesive film extends to cover the side wall of the first upper conductive pad that is not inserted into the first bump structure, and A semiconductor package in which the first thickness of the first upper conductive pad is greater than the second thickness of the first adhesive film.
  2. In Article 1, A semiconductor package in which the first thickness is 1.2 to 1.5 times the second thickness.
  3. In Article 1, The first semiconductor chip has a first width in the first direction, The second semiconductor chip has a second width in the first direction, A semiconductor package in which the first width is larger than the second width.
  4. In Paragraph 3, The first adhesive film is a semiconductor package having a first width equal to the first semiconductor chip in the first direction.
  5. In Paragraph 3, The first bump protective film has a second width equal to the second semiconductor chip in the first direction, One sidewall of the first bump protective film is aligned with one sidewall of the second semiconductor chip in a semiconductor package.
  6. In Article 1, The above first bump structure is: A first solder pattern on the first upper conductive pad; and It includes a first metal pattern on the first solder pattern, The first edge of the first upper conductive pad is a semiconductor package inserted into the first solder pattern.
  7. In Article 6, The first solder pattern has a second edge adjacent to the first semiconductor chip, and The second edge is spaced apart from the first edge in the first direction, and The second edge is a semiconductor package located at a lower level than the first edge.
  8. A first semiconductor chip and a second semiconductor chip stacked in sequence; A first bump protective film interposed between the first and second semiconductor chips and extending in a first direction; A first bump structure that penetrates the first bump protective film and is disposed between the first and second semiconductor chips and connects them; and A first adhesive film interposed between the first bump protective film and the first semiconductor chip, comprising: The first semiconductor chip comprises a first substrate including a first front surface and a first rear surface opposite to each other, a first upper conductive pad disposed on the first rear surface, and a first lower conductive pad disposed on the first front surface. The second semiconductor chip comprises a second substrate including a second front surface and a second rear surface opposite to each other, and a second lower conductive pad disposed on the second front surface. The first bump structure comprises a first solder pattern connected to the first upper conductive pad, and a first metal pattern disposed on the first solder pattern and connected to the second lower conductive pad. The first edge of the first upper conductive pad is inserted into the first solder pattern, and A semiconductor package in which a second edge adjacent to the first substrate of the first solder pattern is spaced apart from the first edge in the first direction and is located at a lower level than the first edge.
  9. In Article 8, A semiconductor package in which the width of the first solder pattern in the first direction is greater than the width of the first metal pattern.
  10. Semiconductor chips stacked in sequence; A molding member covering the above semiconductor chips; A bump structure interposed between the above semiconductor chips and connecting them; A bump protective film covering the side of the above-mentioned bump structure; and It includes an adhesive film interposed between the above-mentioned bump protective film and the semiconductor chip located underneath it, The above semiconductor chips are each: A substrate including a front and a back surface opposite each other; A lower conductive pad positioned on the front surface as described above; Through-via penetrating the above substrate; and It includes an upper conductive pad disposed on the rear surface and connected to the through via, The above bump structure connects the upper conductive pad and the lower conductive pad adjacent thereto, and The upper portion of the upper conductive pad is partially inserted into the bump structure, and The above bump protective film comprises at least one of an epoxy resin, an insulating resin, or a thermosetting resin in a semiconductor package.

Description

Semiconductor Package and Method for Manufacturing the Same The present invention relates to a semiconductor package and a method for manufacturing the same. A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. Typically, semiconductor packages are formed by mounting semiconductor dies onto a printed circuit board (PCB) and electrically connecting them using bonding wires or bumps. With the advancement of the electronics industry, various studies are underway to improve the reliability and durability of semiconductor packages. FIG. 1 is a plan view of a semiconductor package according to embodiments of the present invention. FIG. 2 is a cross-sectional view of FIG. 1 taken along the line A-A' according to embodiments of the present invention. Figure 3 is an enlarged view of the 'E1' portion of Figure 2. FIGS. 4a and 4b show plan views of a first upper conductive pad and a first solder pattern according to embodiments of the present invention. Figures 5a and 5b are enlarged views of the 'E2' portion of Figure 2. FIGS. 6a to 6g are cross-sectional views sequentially illustrating the process of manufacturing a first chip structure according to embodiments of the present invention. FIGS. 7a to 7e are cross-sectional views sequentially illustrating the process of manufacturing the semiconductor package of FIG. 2 according to embodiments of the present invention. Figure 8 is an enlarged view of the 'E3' portion of Figure 7c. FIG. 9 is a cross-sectional view of FIG. 1 taken along the line A-A' according to embodiments of the present invention. Figure 10 is an enlarged view of the 'E4' portion of Figure 9. FIGS. 11a to 11g are cross-sectional views sequentially illustrating the process of manufacturing a second chip structure according to embodiments of the present invention. FIG. 12 is an enlarged view of the 'E5' portion of FIG. 11f. FIGS. 13a to 13d are cross-sectional views sequentially illustrating the process of manufacturing the semiconductor package of FIG. 9 according to embodiments of the present invention. FIG. 14 is an enlarged view of the 'E6' portion of FIG. 13b. FIG. 15 is a cross-sectional view of a semiconductor package according to embodiments of the present invention. Hereinafter, in order to explain the present invention more specifically, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings. FIG. 1 is a plan view of a semiconductor package according to embodiments of the present invention. FIG. 2 is a cross-sectional view of FIG. 1 taken along the line A-A’ according to embodiments of the present invention. Referring to FIG. 1 and FIG. 2, a semiconductor package (1000) according to the embodiments may include first to fifth semiconductor chips (100, 200a to 200d) stacked in sequence, bump structures (BM) disposed between the first to fifth semiconductor chips (100, 200a to 200d) and connecting them, bump protective films (SSP) between the first to fifth semiconductor chips (100, 200a to 200d), and a molding member (MD) covering them. Each of the first to fourth semiconductor chips (100, 200a to 200c) may include an adhesive film (AD) disposed on the rear surface. In the first direction (D1), the first width (W1) of the first semiconductor chip (100) may be larger than the second width (W2) of the second to fifth semiconductor chips (200a, 200b, 200c, 200d). The first semiconductor chip (100) may be, for example, a logic circuit chip. The first semiconductor chip (100) may be, for example, a logic circuit chip. The first semiconductor chip (100) may operate as an interface circuit between the second to fifth semiconductor chips (200a to 200d) and an external controller. The first semiconductor chip (100) may receive commands, data, signals, etc. transmitted from an external controller and transmit the received commands, data, signals, etc. to the second to fifth semiconductor chips (200a to 200d). Alternatively, although not illustrated, the first semiconductor chip (100) may be a buffer chip or an interposer die that does not include a transistor. The first semiconductor chip (100) may be a different type of chip from the second to fifth semiconductor chips (200a, 200b, 200c, 200d). Second to fifth semiconductor chips (200a to 200d) may be stacked sequentially on a first semiconductor chip (100). The second to fifth semiconductor chips (200a to 200d) may be identical memory chips. The memory chips may be, for example, DRAM, NAND Flash, SRAM, MRAM, PRAM, or RRAM. The width of the first semiconductor chip (100) may be wider than the width of the second to fifth semiconductor chips (200a to 200d). In this example, a structure in which one logic circuit chip and four memory chips are stacked is disclosed, but the number of stacked logic circuit chips and memory chips is not limited to this and may vary. For example, eight or more memory chips may be stacked. A first