KR-20260062320-A - SEMICONDUCTOR PACKAGE SUBSTRATE OF ULTRA-FINE VIA STRUCTURE USING PHOTOSENSITIVE FILM AND METHOD OF MANUFACTURING THE SAME

KR20260062320AKR 20260062320 AKR20260062320 AKR 20260062320AKR-20260062320-A

Abstract

In order to overcome the size limitations of via hole processing in laser drilling, a substrate for a semiconductor package having an ultrafine via structure using a photosensitive film and a method for manufacturing the same are disclosed, which can produce a high-performance product by forming an ultrafine via electrode having a fine line width of 10 μm or less using a photosensitive film. A substrate for a semiconductor package having an ultrafine via structure using a photosensitive film according to the present invention comprises: a core layer; at least one insulating layer laminated on the core layer; and a circuit wiring having a first circuit pattern disposed on one side of the insulating layer, a second circuit pattern disposed on the other side of the insulating layer, and a via electrode disposed inside the insulating layer to electrically connect the first and second circuit patterns; wherein the via electrode has a first end that contacts the first circuit pattern and a second end that contacts the second circuit pattern, and the line width of the first end of the via electrode and the line width of the second end of the via electrode satisfy the following Equation 1. Equation 1: 1 ≤ d1 / d2 ≤ 1.1 (Here, d1 is the linewidth of the first end of the via electrode, and d2 is the linewidth of the second end of the via electrode.)

Inventors

임윤호
박건희
유문상

Assignees

주식회사 심텍

Dates

Publication Date: 20260507
Application Date: 20241029

Claims (18)

Core layer; At least one insulating layer laminated on the core layer; and A circuit wiring comprising a first circuit pattern disposed on one surface of the insulating layer, a second circuit pattern disposed on the other surface of the insulating layer, and via electrodes disposed inside the insulating layer to electrically connect the first and second circuit patterns; The above via electrode has a first end in contact with a first circuit pattern and a second end in contact with a second circuit pattern, and Characterized that the line width of the first end of the via electrode and the line width of the second end of the via electrode satisfy the following Equation 1. A substrate for a semiconductor package with an ultrafine via structure using a photosensitive film. Equation 1: 1 ≤ d1 / d2 ≤ 1.1 (Here, d1 is the linewidth of the first end of the via electrode, and d2 is the linewidth of the second end of the via electrode.)
In paragraph 1, At least one insulating layer is laminated on the upper and lower surfaces of the core layer, respectively, and The above circuit wiring is characterized by being formed in an insulating layer, A substrate for a semiconductor package with an ultrafine via structure using a photosensitive film.
In paragraph 1, Characterized that the line width of the first end of the via electrode and the line width of the second end of the via electrode are mutually identical. A substrate for a semiconductor package with an ultrafine via structure using a photosensitive film.
In paragraph 1, The above via electrode is characterized by having a line width of 10㎛ or less, A substrate for a semiconductor package with an ultrafine via structure using a photosensitive film.
In paragraph 1, The above circuit wiring is Characterized by further including a metal seed pattern disposed between the insulating layer and the first circuit pattern. A substrate for a semiconductor package with an ultrafine via structure using a photosensitive film.
In paragraph 5, By the fact that the line width of the first end of the via electrode and the line width of the second end of the via electrode satisfy Equation 1, Characterized by improved adhesion strength between the first end of the via electrode and the metal seed pattern, A substrate for a semiconductor package with an ultrafine via structure using a photosensitive film.
In paragraph 1, A solder mask pattern covering the insulating layer and circuit wiring, and having an opening that exposes a part of the second circuit pattern; Characterized by further including, A substrate for a semiconductor package with an ultrafine via structure using a photosensitive film.
In Paragraph 7, The above solder mask pattern is Characterized by being formed of one or more materials selected from PSR (photo solder resist), liquid photosensitive coverlay, photo polyimide film, and epoxy resin. A substrate for a semiconductor package with an ultrafine via structure using a photosensitive film.
A step of forming a first circuit pattern on a core layer; A step of attaching a first photosensitive film to a core layer on which a first circuit pattern is formed, and then selectively removing a portion of the first photosensitive film to form a first via hole that exposes a portion of the first circuit pattern; A step of forming a via electrode connected to the first circuit pattern within the first via hole of the first photosensitive film; A step of removing the first photosensitive film from the core layer on which the via electrode is formed, and then forming an insulating layer covering the via electrode, the first circuit pattern, and the core layer; A step of performing surface flattening by removing a portion of the surface of the insulating layer to expose the surface of the via electrode, and then attaching a second photosensitive film covering the exposed via electrode and the insulating layer; A step of selectively removing the second photosensitive film to form a second via hole that exposes a portion of the via electrode and the insulating layer; A step of forming a second circuit pattern connected to the via electrode on the via electrode and insulating layer exposed by the second via hole; and A step of removing the second photosensitive film from the core layer on which the second circuit pattern is formed; Characterized by including, Method for manufacturing a substrate for a semiconductor package with an ultrafine via structure using a photosensitive film.
In Paragraph 9, The above first circuit pattern forming step is, A step of sequentially stacking and forming a metal seed layer and a metal circuit layer on a core layer; and A step of sequentially patterning the metal seed layer and the metal circuit layer to form a metal seed pattern and a first circuit pattern; Characterized by including, Method for manufacturing a substrate for a semiconductor package with an ultrafine via structure using a photosensitive film.
In Paragraph 9, By controlling the thickness of the first photosensitive film, Characterized by the height of the above via electrode being adjustable, Method for manufacturing a substrate for a semiconductor package with an ultrafine via structure using a photosensitive film.
In Paragraph 9, The above surface flattening is Characterized by using one or more selected from grinding polishing and chemical mechanical polishing, Method for manufacturing a substrate for a semiconductor package with an ultrafine via structure using a photosensitive film.
In Paragraph 9, The above via electrode has a first end in contact with a first circuit pattern and a second end in contact with a second circuit pattern, and Characterized that the line width of the first end of the via electrode and the line width of the second end of the via electrode satisfy the following Equation 1. Method for manufacturing a substrate for a semiconductor package with an ultrafine via structure using a photosensitive film. Equation 1: 1 ≤ d1 / d2 ≤ 1.1 (Here, d1 is the linewidth of the first end of the via electrode, and d2 is the linewidth of the second end of the via electrode.)
In Paragraph 13, Characterized that the line width of the first end of the via electrode and the line width of the second end of the via electrode are mutually identical. Method for manufacturing a substrate for a semiconductor package with an ultrafine via structure using a photosensitive film.
In Paragraph 13, The above via electrode is characterized by having a line width of 10㎛ or less, Method for manufacturing a substrate for a semiconductor package with an ultrafine via structure using a photosensitive film.
In either of Paragraph 10 or Paragraph 13, By the fact that the line width of the first end of the via electrode and the line width of the second end of the via electrode satisfy Equation 1, Characterized by improved adhesion strength between the first end of the via electrode and the metal seed pattern, Method for manufacturing a substrate for a semiconductor package with an ultrafine via structure using a photosensitive film.
In Paragraph 9, After the second circuit pattern formation step above, A step of forming a solder mask pattern that covers the second circuit pattern and the insulating layer and has an opening that exposes a portion of the second circuit pattern; Characterized by further including, Method for manufacturing a substrate for a semiconductor package with an ultrafine via structure using a photosensitive film.
In Paragraph 16, The above solder mask pattern is Characterized by being formed of one or more materials selected from PSR (photo solder resist), liquid photosensitive coverlay, photo polyimide film, and epoxy resin. Method for manufacturing a substrate for a semiconductor package with an ultrafine via structure using a photosensitive film.

Description

Semiconductor package substrate of ultra-fine via structure using photosensitive film and method of manufacturing the same The present invention relates to a substrate for a semiconductor package having an ultrafine via structure using a photosensitive film and a method for manufacturing the same. More specifically, in order to overcome the size limit of via hole processing by laser drilling, the invention relates to a substrate for a semiconductor package having an ultrafine via electrode having a fine line width of 10 μm or less using a photosensitive film and a method for manufacturing the same, which enables the production of a high-performance product. Conventional laser drill via fill processing methods irradiate a laser beam directly onto prepreg to melt the prepreg within a certain range and perform post-processing steps such as dry plasma and wettable de-smear to remove the smear remaining in the via holes. Subsequently, the interlayer circuit pattern is electrically connected via via electrodes through chemical copper and copper plating. In the copper plating, thickness variations occur due to factors such as the density of the circuit pattern and via holes, shielding, and process deviations. In conclusion, conventionally, when manufacturing via electrodes for electrically connecting interlayer circuit patterns of printed circuit boards, a laser beam with high energy density is utilized, so via electrodes can be formed stably; however, due to the high processing energy and the need for smear treatment, the reduction of via hole size is limited, and there is a variation in copper thickness depending on the location. A relevant prior art document is Korean Patent Publication No. 10-2017-0087302 (published July 28, 2017), which discloses a method for manufacturing a multilayer circuit board in which microvias are formed. FIG. 1 is a cross-sectional view showing a substrate for a general semiconductor package. FIG. 2 is a cross-sectional view showing an enlarged view of the "2" portion of FIG. 1. FIG. 3 is a cross-sectional view showing a substrate for a semiconductor package with an ultrafine via structure using a photosensitive film according to an embodiment of the present invention. FIG. 4 is a cross-sectional view showing an enlarged view of the "4" portion of FIG. 3. FIGS. 5 to 16 are process cross-sectional views illustrating a method for manufacturing a substrate for a semiconductor package having an ultrafine via structure using a photosensitive film according to an embodiment of the present invention. The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Throughout the specification, the same reference numerals refer to the same components. The following is a detailed description of a substrate for a semiconductor package having an ultrafine via structure using a photosensitive film according to a preferred embodiment of the present invention and a method for manufacturing the same, with reference to the attached drawings. FIG. 1 is a cross-sectional view showing a substrate for a general semiconductor package, and FIG. 2 is a cross-sectional view showing an enlarged view of the "2" portion of FIG. 1. As shown in FIGS. 1 and 2, a substrate (1) for a general semiconductor package includes a core layer (10), an insulating layer (20), and circuit wiring (40). Here, the core layer (10) has an upper surface (10a) and a lower surface (10b) opposite to the upper surface (10a). At least one insulating layer (20) is laminated on the core layer (10). This insulating layer (20) has one side (20a) and another side (20b) opposite to the one side (20a). At this time, the one side (20a) of the insulating layer (20) is bonded to the upper surface (10a) of the core layer (10). The circuit wiring (40) has a first circuit pattern (42), a second circuit pattern (44), and via electrodes (46). Here, the first circuit pattern (42) is placed on one side (20a) of the insulating layer (20), and the second circuit pattern (44) is placed on the other side (20b) of the insulating layer (20). The via electrode (46) is placed inside the insulating layer (20) and electrically connects the first and second circuit patterns (42, 44). These via electrodes (46) can be formed within a via hole (not shown) that penetrates a part of the insulating layer (20). In order to form via electrodes (46), the above-described general semiconductor package substrate (1) undergoes post-processing processes such as dry