KR-20260062422-A - MEMORY DEVICE, MEMORY SYSTEM COMPRISING MEMORY DEVICE, AND OPERATING METHOD THEREOF

Abstract

A memory device, a memory system including the memory device, and a method of operating the same are provided. The memory device includes a first volatile memory including a first logical memory device, and a CXL memory controller that controls the operation of the first volatile memory and receives a request regarding the first volatile memory through a CXL interface including a CXL switch from a host. The first logical memory device includes a plurality of segments that are physically separated from each other, and at least two of the plurality of segments form a single memory unit. The CXL memory controller includes a Coarse-grained Global Counter that counts the number of requests received per memory unit of the first logical memory device and stores a count value; a Global Hotness Monitor that determines whether each memory unit of the first logical memory device is a hot unit or a cold unit based on the count value; a Hotness Tracker Controller that generates a first bit map per memory unit included in the first logical memory device based on the determination result of the Global Hotness Monitor; and a first Hotness Tracker that determines whether data stored per multiple segment unit included in the first logical memory device is hot based on the first bit map.

Inventors

• 이원재
• 남호진
• 소진인

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20241029

Claims (20)

1. A first volatile memory including a first logical memory device; and A CXL memory controller that controls the operation of the first volatile memory and receives a request regarding the first volatile memory from a host through a CXL interface including a CXL switch, and The first logical memory device includes a plurality of segments that are physically separated from each other, and At least two of the above plurality of segments constitute a single memory unit, and The above CXL memory controller is, A coarse-grained global counter that counts the number of requests received per memory unit of the first logical memory device and stores the count value; A global hotness monitor that determines whether a unit is a hot unit or a cold unit for each memory unit of the first logical memory device based on the above count value; A hotness tracker controller that generates a first bitmap for each memory unit included in the first logical memory device based on the judgment result of the global hotness monitor; and A memory device comprising a first hotness tracker that determines whether data stored in a plurality of segment units included in the first logical memory device is hotness based on the first bit map.
2. In paragraph 1, The first hotness tracker, in response to determining that the first data stored in the first segment among the plurality of segments included in the first logical memory device is hot based on the first bitmap, causes the first data to be stored in the second volatile memory of the host, and A memory device in which the host and the second volatile memory are not connected via the CXL interface.
3. In paragraph 2, A memory device in which the above host and the above second volatile memory communicate with each other through a DDR (Double Data Rate) interface.
4. In paragraph 1, The above hotness tracker controller includes a power management module that manages the power supplied to the first hotness tracker, and The power management module above responds to the global hotness monitor determining that all of the plurality of memory units included in the first logical memory device are the cold units, A memory device that turns off the power supplied to the first hotness tracker.
5. In paragraph 1, The above hotness tracker controller includes a filtering module, and The filtering module above responds to the determination that the first memory unit among the plurality of memory units included in the first logical memory device is the cold unit, A memory device that initializes bits on the first bit map of a plurality of segments included in the first memory unit.
6. In paragraph 5, The first hotness tracker responds to the initialization of bits on the first bitmap of a plurality of segments included in the first memory unit, A memory device that does not determine whether the data stored in each of the plurality of segments included in the first memory unit is hot.
7. In paragraph 1, The first logical memory device includes a first memory unit and a second memory unit having different physical addresses, and The above global hotness monitor is, If the first count value for the first memory unit is smaller than the cold threshold, the first memory unit is determined to be the cold unit, and If the second count value for the second memory unit is greater than the hot threshold, the second memory unit is determined to be the hot unit, and The above cold threshold and the above hot threshold are preset by the host, in a memory device.
8. In paragraph 1, The first logical memory device includes a first memory unit comprising a first segment and a second segment having different physical addresses, and The first hotness tracker determines that the data stored in the first and second segments is hot when the request received for the first memory unit exceeds a hot threshold per epoch, and The above hotness tracker controller includes a sampling module, and A memory device in which the sampling module, in response to the global hotness monitor determining that the first memory unit is the hot unit, samples some of the requests for the first memory unit in the next epoch and transmits them to the first hotness tracker.
9. In paragraph 8, The above hot threshold is a memory device that is preset by the host.
10. In paragraph 1, The first logical memory device includes a first memory unit determined to be the hot unit by the global hotness monitor, and The above hotness tracker controller is a memory device that transmits the request received by the first memory unit to the first hotness tracker.
11. In Paragraph 10, A memory device in which the first hotness tracker counts the number of received requests and determines whether the data stored in the first memory unit is hotness by the plurality of segment units.
12. In Paragraph 10, The first memory unit includes the first segment and the second segment, and The above hotness tracker controller includes a sampling module, and A memory device in which the sampling module transmits only some of the requests received by the first memory unit to the first hotness tracker in response to the number of requests received per epoch for the first memory unit being greater than a hot threshold set by the host.
13. In paragraph 1, The above first volatile memory further includes a second logical memory device, and The second logical memory device includes a plurality of segments that are physically separated from each other, and At least two of the above plurality of segments constitute a single memory unit, and The above-mentioned coarse-grain global counter counts the number of requests received per memory unit of the second logical memory device and stores a count value, and The global hotness monitor determines whether the second logical memory device is a hot unit or a cold unit for each memory unit of the second logical memory device based on the count value for the second logical memory device, and The above hotness tracker controller generates a second bitmap for each memory unit included in the second logical memory device based on the judgment result of the global hotness monitor, and A memory device comprising a second hotness tracker that determines whether the data stored in the plurality of segment units included in the second logical memory device is hotness based on the second bit map, wherein the above CXL memory controller further comprises the second hotness tracker.
14. Host; A first CXL memory device comprising a first volatile memory including a first logical memory device and a first CXL memory controller controlling the operation of the first volatile memory; and It includes a CXL switch that provides an interface between the host and the first CXL memory device, and The above host transmits a first request regarding the first volatile memory through the CXL switch, and The first logical memory device includes a plurality of segments that are physically separated from each other, and At least two of the above plurality of segments constitute a single memory unit, and The above CXL switch is, A coarse-grained global counter that counts the number of first requests received per memory unit of the first logical memory device and stores a count value; A global hotness monitor that determines whether a unit is a hot unit or a cold unit for each memory unit of the first logical memory device based on the above count value; and It includes a hotness tracker controller that generates a first bitmap for each memory unit included in the first logical memory device based on the judgment result of the global hotness monitor, and A memory system comprising a first CXL memory controller that determines whether data stored in a plurality of segment units included in the first logical memory device is hot based on the first bit map.
15. In Paragraph 14, The second volatile memory including the second logical memory device and the second CXL memory device including a second CXL memory controller that controls the operation of the second volatile memory further include the second CXL memory device. The above CXL switch further provides an interface between the host and the second CXL memory device, and The above host transmits a second request regarding the second volatile memory through the CXL switch, and The second logical memory device includes a plurality of segments that are physically separated from each other, and At least two of the above plurality of segments constitute a single memory unit, and The above-mentioned coarse-grain global counter counts the number of the second requests received per memory unit of the second logical memory device and stores a count value, and The global hotness monitor determines whether the second logical memory device is a hot unit or a cold unit for each memory unit of the second logical memory device based on the count value for the second logical memory device, and The above hotness tracker controller generates a second bitmap for each memory unit included in the second logical memory device based on the judgment result of the global hotness monitor, and A memory system comprising a second CXL memory controller that further includes a second hotness tracker for determining whether data stored in a plurality of segment units included in the second logical memory device is hotness based on the second bit map.
16. In paragraph 15, The second hotness tracker, in response to determining that the first data stored in the first segment among the plurality of segments included in the second logical memory device is hot based on the second bitmap, causes the first data to be stored in the third volatile memory of the host, and A memory system in which the above host and the above second volatile memory communicate with each other through a DDR (Double Data Rate) interface.
17. In paragraph 15, The first logical memory device includes a first memory unit determined to be the hot unit by the global hotness monitor, and The second logical memory device includes a second memory unit determined to be the hot unit by the global hotness monitor, and A memory system in which the above-described hotness tracker controller transmits the request received by the first memory unit to the first hotness tracker and transmits the request received by the second memory unit to the second hotness tracker.
18. A memory system comprising a host, a volatile memory including a logical memory device, a CXL memory controller controlling the operation of the volatile memory, and a CXL switch providing an interface between the host and the CXL memory controller, is provided. By the above host, a request regarding the volatile memory is transmitted to the CXL memory controller through the CXL switch, and By means of a Coarse-grained Global Counter, the number of requests received per memory unit of the logical memory device is counted and a count value is stored, and By the global hotness monitor, it is determined whether each memory unit of the logical memory device is a hot unit or a cold unit based on the count value, and A bit map is generated for each memory unit included in the logical memory device by the hotness tracker controller based on the judgment result of the global hotness monitor, and The hotness tracker determines whether the data stored in the plurality of segment units included in the logical memory device is hot based on the bitmap. A method of operation of a memory system in which at least two of the plurality of segments constitute one memory unit.
19. In Paragraph 18, A method of operation of a memory system, wherein the above-mentioned coarse-grained global counter, the above-mentioned global hotness monitor, and the above-mentioned hotness tracker controller are positioned at the CXL switch level, and the above-mentioned hotness tracker is positioned inside a memory device including the above-mentioned CXL memory controller and the above-mentioned volatile memory.
20. In Paragraph 18, The above CXL memory controller and the above volatile memory are placed inside a memory device, and A method of operation of a memory system comprising the above memory device, the above coarse-grain global counter, the above global hotness monitor, the above hotness tracker controller, and the above hotness tracker.

Description

Memory device, memory system comprising memory device, and method of operating the same The present invention relates to a memory device, a memory system including a memory device, and a method of operating the same. With the advancement of technologies such as artificial intelligence (AI), big data, and edge computing, there is a growing demand to process larger amounts of data more quickly on devices. In other words, high-bandwidth applications performing complex calculations require faster data processing and more efficient memory access. However, host devices, including computing units such as CPUs and GPUs, are mostly connected to semiconductor devices containing memory via the PCIe protocol, resulting in relatively low bandwidth and long latency, as well as issues with memory sharing and consistency with the semiconductor devices. Consequently, the Compute Express Link Interface (CXL), which signifies a low-latency and high-bandwidth link, is being utilized. Meanwhile, if data stored in a CXL memory device that communicates with the host through a CXL interface is frequently accessed by the host, a CXL memory hotness tracking function may be provided to migrate the data to the host's DDR (double data rate) memory. FIG. 1 is an exemplary drawing for illustrating a memory system according to some embodiments. FIG. 2 is an exemplary drawing for explaining in detail the components of the host and CXL memory device of FIG. 1. Figure 3 is a diagram showing the configuration of the CXL memory device illustrated in Figures 1 and 2. Figure 4 is a diagram showing an example of a memory cell in the CXL memory device of Figure 3. FIG. 5 is a drawing for illustrating a memory system according to some embodiments. Figure 6 is a diagram illustrating the memory device of Figure 5. FIGS. 7 and FIGS. 8 are drawings for illustrating a logical memory device according to some embodiments. FIG. 9 is a flowchart for explaining the operation of a memory system according to some embodiments. FIG. 10 is a flowchart illustrating the operation of a coarse-grain global counter according to some embodiments. FIG. 11 is a flowchart illustrating the operation of a global hotness monitor according to some embodiments. FIG. 12 is a flowchart for explaining the operation of a hotness tracker controller according to some embodiments. FIGS. 13 to 15 are drawings for explaining the operation of a hotness tracker controller according to some embodiments. FIG. 16 is a diagram illustrating a bitmap generated by a hotness tracker controller according to some embodiments. FIGS. 17 and FIGS. 18 are drawings for illustrating a logical memory device according to some embodiments. FIG. 19 is a diagram illustrating the operation of a hotness tracker controller according to some embodiments. FIG. 20 is a diagram illustrating a bitmap generated by a hotness tracker controller according to some embodiments. FIG. 21 is a drawing for illustrating a memory system according to some embodiments. FIGS. 22 and FIGS. 23 are drawings for illustrating a memory system according to some embodiments. FIG. 24 is a drawing for illustrating a memory system according to some embodiments. FIG. 25 is a drawing for explaining the effects of a memory device according to some embodiments. FIG. 26 is a diagram showing a computing system according to some embodiments. FIG. 27 is an exemplary drawing for illustrating a data center to which a computing system according to some embodiments is applied. Hereinafter, a memory device, a memory system, and a method of operation according to several embodiments will be described with reference to the attached drawings. FIG. 1 is an exemplary drawing for illustrating a memory system according to some embodiments. Referring to FIG. 1, the memory system (100) may include a host (101), a CXL (Compute Express Link) memory device (110), volatile memories (102a, 102b), and a CXL switch (103). In some embodiments, the memory system (100) may be included in user devices such as a personal computer, a laptop computer, a server, a media player, a digital camera, etc., or in automotive devices such as navigation, a black box, an automotive electronic device, etc. Alternatively, the memory system (100) may be a mobile system such as a mobile phone, a smartphone, a tablet personal computer, a wearable device, a healthcare device, or an IoT (Internet of Things) device. The host (101) can control the overall operation of the memory system (100). In some embodiments, the host (101) may be one of various processors such as a CPU (central processing unit), a GPU (graphics processing unit), an NPU (neural processing unit), a DPU (data processing unit), etc. In some embodiments, the host (101) may include a single-core processor or a multi-core processor. Volatile memories (102a, 102b) may be used as main memory or system memory of a memory system (100). Volatile memories (102a, 102b) may be connected to a host (101). In some embodiments, each of the vol