KR-20260062509-A - SEMICONDUCTOR PACKAGE

KR20260062509AKR 20260062509 AKR20260062509 AKR 20260062509AKR-20260062509-A

Abstract

A semiconductor package comprises a package substrate, a semiconductor chip disposed on an upper surface of the package substrate having a first surface facing the package substrate and a second surface opposite to the first surface and having a first coefficient of thermal expansion, a stress control layer applied on the second surface of the semiconductor chip having a second coefficient of thermal expansion greater than the first coefficient of thermal expansion to have residual stress in the compression direction, and a sealing member covering the semiconductor chip and the stress control layer on the upper surface of the package substrate.

Inventors

지소현
유인희

Assignees

삼성전자주식회사

Dates

Publication Date: 20260507
Application Date: 20241029

Claims (10)

Package substrate; A semiconductor chip disposed on the upper surface of the package substrate, having a first surface facing the package substrate and a second surface opposite to the first surface, and having a first coefficient of thermal expansion; A stress control layer applied on the second surface of the semiconductor chip and having a second thermal expansion coefficient greater than the first thermal expansion coefficient to have residual stress in the compression direction; and A semiconductor package comprising a sealing member covering the semiconductor chip and the stress control layer on the upper surface of the package substrate.
In claim 1, the stress control layer comprises a ceramic material in a semiconductor package.
In claim 2, the stress control layer comprises any one of alumina ( Al₂O₃ ), zirconia ( ZrO₂ ) , and aluminum nitride (AlN) in a semiconductor package.
In claim 1, the stress control layer is a semiconductor package having a thickness of 5 μm to 20 μm.
A semiconductor package according to claim 1, wherein the second coefficient of thermal expansion is within the range of 4.0× 10⁻⁶ /℃ to 20× 10⁻⁶ ℃.
In claim 1, the package substrate has a plurality of substrate pads on an upper surface, and the semiconductor chip has a plurality of chip pads on a second surface, A semiconductor package further comprising bonding wires that electrically connect the plurality of chip pads and the plurality of substrate pads.
In claim 1, the package substrate has a plurality of substrate pads on an upper surface, and the semiconductor chip has a plurality of chip pads on a first surface, A semiconductor package further comprising conductive connection members that electrically connect the plurality of chip pads and the plurality of substrate pads.
In Article 1, A semiconductor package further comprising a second stress control layer applied on the upper surface of the sealing member and having a third thermal expansion coefficient greater than the first thermal expansion coefficient to have residual stress in the compression direction.
In claim 8, the second stress control layer comprises one of alumina ( Al₂O₃ ), zirconia ( ZrO₂ ), and aluminum nitride (AlN) , in a semiconductor package.
Package substrate; A semiconductor chip disposed on the upper surface of the above-mentioned package substrate and having a first coefficient of thermal expansion; A sealing member covering the semiconductor chip on the upper surface of the package substrate; and A semiconductor package comprising a stress control layer applied on the upper surface of the sealing member and having a second thermal expansion coefficient greater than the first thermal expansion coefficient to have residual stress in the compression direction.

Description

Semiconductor Package The present invention relates to a semiconductor package and a method for manufacturing a semiconductor package, and more specifically, to a semiconductor package manufactured through a bending test and a method for manufacturing the same. In the manufacture of a semiconductor package, after a semiconductor chip is mounted on a package substrate, a sealing member, such as an epoxy mold compound (EMC), can be formed to protect it from external environments such as heat and moisture. Subsequently, a three-point bending test can be performed to measure mechanical properties of the semiconductor package, such as the flexural modulus, flexural strength, and flexural yield strength. In the three-point bending test, a load can be applied to the package substrate to induce bending. At this time, tensile stress is generated in the semiconductor chip, which may cause cracks to occur in the semiconductor chip or the sealing member. FIG. 1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. FIGS. 2 to 5 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. Figure 6a is a cross-sectional view showing the bending deformation of a semiconductor package in the three-point bending test of Figure 5. FIG. 6b is a cross-sectional view showing the stresses applied to the semiconductor chip of the semiconductor package of FIG. 6a. FIG. 7 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. FIG. 8 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. FIG. 1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. Referring to FIG. 1, the semiconductor package (100) may include a package substrate (110), a semiconductor chip (200), a stress control layer (300), and a sealing member (400). Additionally, the semiconductor package (100) may further include external connection members (160). In exemplary embodiments, the package substrate (110) may be a substrate having an upper surface (112) and a lower surface (114) facing each other. For example, the package substrate (110) may include a printed circuit board (PCB), a flexible substrate, a tape substrate, etc. The printed circuit board may be a multilayer circuit board having vias and various circuits inside. The package substrate (110) may include internal wiring as channels for electrical connection with a semiconductor chip (200). The package substrate (110) may include a first side (S1) and a second side (S2) that extend in a direction parallel to the second direction (Y direction) and face each other, and a third side and a fourth side that extend in a direction parallel to the first direction (X direction) which is orthogonal to the second direction and face each other. The package substrate (110) may have a chip mounting area in the center region. The chip mounting area may be an area where a semiconductor chip (200) is mounted. The chip mounting area may have a rectangular shape. The package substrate (110) may include substrate pads (120) arranged along one side (S1, S2) of the package substrate (110). The substrate pads (120) may each be connected to the wiring. The wiring may extend from the upper surface (112) or inside the package substrate (110). For example, at least a portion of the wiring may be used as a landing pad and as a substrate pad. Although only a few substrate pads are illustrated in the drawings above, it will be understood that the number, shape, and arrangement of the substrate pads are provided as examples and that the present invention is not limited thereto. A first insulating film (130) that exposes substrate pads (120) may be formed on the upper surface (112) of the package substrate (110). The first insulating film (130) may cover the entire upper surface (112) of the package substrate (110) excluding the substrate pads (120). For example, the first insulating film may include a solder resist. In exemplary embodiments, the semiconductor chip (200) may be mounted on the chip mounting area of the package substrate (110). The semiconductor chip (200) may be mounted on the package substrate (110) by a wire bonding method. The semiconductor chip (200) may be positioned such that the first surface (202) on which the chip pads (210) are formed, i.e., the opposite surface (204) of the active surface, faces the package substrate (110). The first semiconductor chip (200) may have a rectangular shape having four sides when viewed in a plan view. The first semiconductor chip (200) may include a first side (E1) and a second side (E2) that face each other and extend in a direction parallel to the first direction (X direction), and a third side and a fourth side (E4a) that face ea