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KR-20260062579-A - Integrated circuit device

KR20260062579AKR 20260062579 AKR20260062579 AKR 20260062579AKR-20260062579-A

Abstract

An integrated circuit element comprises a first transistor including a first channel region and a first source/drain region connected to the first channel region, a second transistor including a second channel region and a second source/drain region connected to the second channel region, a first contact structure connected to the first source/drain region, and a second contact structure connected to the second source/drain region, wherein the first contact structure and the second contact structure are each composed of at least two metal-containing films, the first contact structure includes a first major metal plug having the largest volume among the at least two metal-containing films included in the first contact structure, and the second contact structure includes a second major metal plug having the largest volume among the at least two metal-containing films included in the second contact structure, wherein the first major metal plug and the second major metal plug are made of different metals, and the cross-sectional shape of the first major metal plug and the cross-sectional shape of the second major metal plug are different from each other.

Inventors

  • 정혜원
  • 김근우
  • 김완돈
  • 최선규
  • 김민규
  • 정상훈

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260507
Application Date
20241029

Claims (10)

  1. A first transistor comprising a first channel region and a first source/drain region connected to the first channel region, and A second transistor comprising a second channel region and a second source/drain region connected to the second channel region, and A first contact structure connected to the first source/drain region, and It includes a second contact structure connected to the second source/drain region, and The first contact structure and the second contact structure are each composed of at least two metal-containing films, and The first contact structure comprises a first major metal plug having the largest volume among the at least two metal-containing films included within the first contact structure, and The second contact structure comprises a second major metal plug having the largest volume among the at least two metal-containing films included within the second contact structure, and The first major metal plug and the second major metal plug are made of different metals, and the cross-sectional shape of the first major metal plug and the cross-sectional shape of the second major metal plug are different from each other.
  2. In paragraph 1, The first transistor is an NMOS (n-channel metal-oxide semiconductor) transistor, and the second transistor is a PMOS (p-channel metal-oxide semiconductor). In the first contact structure above, the first major metal plug has a U-shaped cross-sectional shape that defines the internal space, The second major metal plug in the second contact structure is an integrated circuit element having a pillar shape filled with a single metal without interruption along a horizontal direction from the outer surface of the second major metal plug to the inner center.
  3. In paragraph 2, The above first contact structure is A first minor metal plug that fills the internal space defined by the first major metal plug and contacts the inner surface of the first major metal plug, and is made of a metal of a different type from the metal included in the first major metal plug, and An integrated circuit element further comprising a first conductive barrier metal-containing film surrounding the first major metal plug and the first minor metal plug, and in contact with the outer surface of the first major metal plug.
  4. In paragraph 2, The above second contact structure is A second minor metal plug having a U-shaped cross-sectional shape to surround the second major metal plug, in contact with the outer surface of the second major metal plug, and made of a metal of a different type from the metal included in the second major metal plug, and An integrated circuit element further comprising a second conductive barrier metal-containing film surrounding the second major metal plug and the second minor metal plug, and in contact with the outer surface of the second minor metal plug.
  5. In paragraph 1, The first transistor is an NMOS transistor, and the second transistor is a PMOS transistor, and In the first contact structure above, the first major metal plug has a pillar shape filled with a single metal without interruption along the horizontal direction from the outer surface of the first major metal plug to the inner center, In the second contact structure above, the second major metal plug is an integrated circuit element having a U-shaped cross-sectional shape that defines an internal space.
  6. In paragraph 1, The first transistor is an NMOS transistor, and the second transistor is a PMOS transistor, and The first major metal plug of the first contact structure and the second major metal plug of the second contact structure each have a pillar shape filled with a single metal without interruption along a horizontal direction from the outer surface to the inner center, An integrated circuit element in which, in the vertical direction, the first length of the first major metal plug of the first contact structure is larger than the second length of the second major metal plug of the second contact structure.
  7. A plurality of channel regions, each composed of a plurality of nanosheets, and, A plurality of gate lines surrounding the above plurality of channel regions, and A first source/drain region comprising a Si layer doped with an n-type dopant that is in contact with the plurality of nanosheets included in the first channel region selected among the plurality of channel regions, and A first contact structure connected to the first source/drain region, and A second source/drain region comprising a SiGe layer doped with a p-type dopant that is in contact with the plurality of nanosheets included in the second channel region selected among the plurality of channel regions, and It includes a second contact structure connected to the second source/drain region, and The first contact structure and the second contact structure are each composed of at least two metal-containing films, and The first contact structure comprises a first major metal plug having the largest volume among the at least two metal-containing films included within the first contact structure, and The second contact structure comprises a second major metal plug having the largest volume among the at least two metal-containing films included within the second contact structure, and The first major metal plug and the second major metal plug are made of different metals, and the cross-sectional shape of the first major metal plug and the cross-sectional shape of the second major metal plug are different from each other.
  8. In Paragraph 7, The first major metal plug is made of a metal that induces tensile strain in the plurality of nanosheets included in the first channel region, and The above second major metal plug is an integrated circuit device made of a metal that induces compressive strain in the plurality of nanosheets included in the second channel region.
  9. In Paragraph 7, The first major metal plug of the first contact structure and the second major metal plug of the second contact structure each have a pillar shape filled with a single metal without interruption along a horizontal direction from the outer surface to the inner center, An integrated circuit element in which, in the vertical direction, the first length of the first major metal plug of the first contact structure is larger than the second length of the second major metal plug of the second contact structure.
  10. A plurality of channel regions, each composed of a plurality of nanosheets, and, An NMOS transistor comprising a first channel region selected among the plurality of channel regions, a first gate line surrounding the plurality of nanosheets included in the first channel region, and a first source/drain region comprising a Si layer in contact with the plurality of nanosheets included in the first channel region and doped with an n-type dopant, A PMOS transistor comprising a second channel region selected among the plurality of channel regions, a second gate line surrounding the plurality of nanosheets included in the second channel region, and a second source/drain region comprising a SiGe layer in contact with the plurality of nanosheets included in the second channel region and doped with a p-type dopant, and A first contact structure connected to the first source/drain region, and It includes a second contact structure connected to the second source/drain region, and The first contact structure and the second contact structure are each composed of at least two metal-containing films, and The first contact structure comprises a first major metal plug having the largest volume among the at least two metal-containing films included within the first contact structure, and The second contact structure comprises a second major metal plug having the largest volume among the at least two metal-containing films included within the second contact structure, and The first major metal plug and the second major metal plug are made of different metals selected from molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), and aluminum (Al), and the cross-sectional shape of the first major metal plug and the cross-sectional shape of the second major metal plug are different, forming an integrated circuit element.

Description

Integrated circuit device The technical concept of the present invention relates to an integrated circuit element, and in particular to an integrated circuit element comprising a metal wiring layer. Due to the advancement of electronic technology, the downscaling of integrated circuit devices is progressing rapidly, and consequently, the linewidth and pitch of metal wiring layers included in integrated circuit devices are also becoming finer. Accordingly, there is a need to develop integrated circuit devices having a metal wiring structure capable of suppressing the increase in resistance of metal wiring layers and improving electrical characteristics and reliability. FIG. 1 is a cross-sectional view for explaining an integrated circuit element according to embodiments of the technical concept of the present invention. FIG. 2 is an enlarged cross-sectional view of the areas labeled "EX1" and "EX2" in FIG. 1. FIGS. 3 to 10 are cross-sectional views illustrating integrated circuit elements according to other embodiments of the technical concept of the present invention. FIGS. 11a to 11h are cross-sectional views illustrated in the order of process to explain a method for manufacturing an integrated circuit element according to embodiments of the technical concept of the present invention. FIGS. 12a to 12e are enlarged cross-sectional views illustrated in the order of process to explain in more detail the method of manufacturing an integrated circuit element according to embodiments of the technical concept of the present invention. FIGS. 13a and FIGS. 13b are cross-sectional views illustrated in the order of process to explain a method for manufacturing an integrated circuit element according to other embodiments of the technical concept of the present invention. FIGS. 14a to 14e are cross-sectional views illustrated in the order of process to explain a method for manufacturing an integrated circuit element according to other embodiments of the technical concept of the present invention. FIGS. 15a to 15d are cross-sectional views illustrated in the order of process to explain a method for manufacturing an integrated circuit element according to other embodiments of the technical concept of the present invention. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted. FIG. 1 is a cross-sectional view for explaining an integrated circuit element (100) according to embodiments of the technical concept of the present invention. FIG. 2 is a cross-sectional view showing an enlarged view of the regions labeled "EX1" and "EX2" in FIG. 1. Referring to FIGS. 1 and 2, an integrated circuit element (100) includes a substrate (102) having a first element region (I) and a second element region (II). The first element region (I) and the second element region (II) of the substrate (102) refer to different regions of the substrate (102) and may be regions that perform different operations on the substrate (102). The first element region (I) and the second element region (II) may be regions spaced apart from each other, or regions connected to each other at adjacent locations. The first device region (I) and the second device region (II) may be regions requiring different threshold voltages. For example, the first device region (I) may be an NMOS (n-channel metal-oxide semiconductor) transistor region, and the second device region (II) may be a PMOS (p-channel metal-oxide semiconductor) transistor region. In exemplary embodiments, the first device region (I) and the second device region (II) may each be a region selected from a memory region and a non-memory region. The memory region may be a region constituting a volatile memory device such as DRAM (Dynamic Random Access Memory) or SRAM (Static RAM), or a non-volatile memory device such as ROM (Read Only Memory), MROM (Mask ROM), PROM (Programmable ROM), EPROM (Erasable ROM), EEPROM (Electrically Erasable ROM), FRAM (Ferromagnetic ROM), PRAM (Phase change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), flash memory, etc. The non-memory region may include a logic region. The logic region may include standard cells that perform desired logical functions, such as a counter or a buffer. The standard cells may include various types of logic cells that include a plurality of circuit elements, such as transistors or registers. The above logic cell can be configured, for example, AND, NAND, OR, NOR, XOR (exclusive OR), XNOR (exclusive NOR), INV (inverter), ADD (adder), BUF (buffer), DLY (delay), FIL (filter), multiplexer (MXT/MXIT), OAI (OR/AND/INVERTER), AO (AND/OR), AOI (AND/OR/INVERTER), D flip-flop, reset flip-flop, master-slave flip-flop, latch, etc. Referring to FIGS. 1 and 2, an integrated circuit device (100) comprising field-effect transistors having a gate-all-around structure inc