KR-20260062580-A - Semiconductor Memory Device

Abstract

A semiconductor memory device according to one embodiment of the present disclosure may include a die in which a plurality of planes, each comprising a plurality of memory cells, are arranged; a plurality of temperature sensors arranged in the die in correspondence with the plurality of planes; and a temperature compensation circuit that generates a read control signal for performing a read operation of the plurality of planes based on plane temperature values obtained from the plurality of temperature sensors.

Inventors

• 박병준
• 김무선
• 박주현

Assignees

• 에스케이하이닉스 주식회사

Dates

Publication Date

20260507

Application Date

20241029

Claims (20)

1. A die having a plurality of planes, each containing a plurality of memory cells; A plurality of temperature sensors arranged corresponding to the plurality of planes in the above die; and A semiconductor memory device comprising a temperature compensation circuit that generates a read control signal for performing a read operation of the plurality of planes based on plane temperature values obtained from the plurality of temperature sensors.
2. In paragraph 1, Each of the plurality of temperature sensors is a semiconductor memory device positioned closest to a corresponding plane among the plurality of planes.
3. In paragraph 1, The above plurality of planes are arranged in a matrix form, and A semiconductor memory device in which each of the above plurality of temperature sensors is positioned closest to a corresponding vertex among the vertices of the die.
4. In paragraph 1, The above-mentioned read control signal is a semiconductor memory device including a read judgment voltage for determining data.
5. In paragraph 4, A semiconductor memory device further comprising a page buffer circuit that determines data by comparing the voltage level of a signal transmitted through a bitline with the read determination voltage.
6. In paragraph 1, A semiconductor memory device comprising a voltage control signal for controlling the level of shift control voltages for shifting the threshold voltage distribution of the memory cells, wherein the above read control signal is a voltage control signal.
7. In paragraph 6, A semiconductor memory device further comprising a voltage generator that generates the shift control voltage based on the above voltage control signal.
8. In paragraph 6, A semiconductor memory device wherein the shift control voltage comprises a wordline voltage applied to a wordline, a drain select line voltage applied to a drain select line, and a source select line voltage applied to a source select line.
9. In paragraph 1, A semiconductor memory device in which, when the above-mentioned plane temperature values are included in the same temperature range, the temperature compensation circuit generates a single read control signal corresponding to the temperature range.
10. In paragraph 1, A semiconductor memory device in which, when the above-mentioned plane temperature values are included in different temperature ranges, the temperature compensation circuit generates a plurality of read control signals corresponding to the temperature ranges.
11. In Paragraph 10, A semiconductor memory device in which a read determination voltage provided to a plane corresponding to a plane temperature value included in a first temperature range is lower than a read determination voltage provided to a plane corresponding to a plane temperature value included in a second temperature range higher than the first temperature range.
12. In Paragraph 10, A semiconductor memory device in which the shift control voltage provided to a plane corresponding to a plane temperature value included in a first temperature range is higher than the shift control voltage provided to a plane corresponding to a plane temperature value included in a second temperature range higher than the first temperature range.
13. In paragraph 1, A semiconductor memory device in which the temperature compensation circuit calculates a representative temperature value by calculating the plane temperature values and generates a read control signal corresponding to the representative temperature value.
14. In Paragraph 13, A semiconductor memory device in which the above representative temperature value is the average of the above plane temperature values.
15. In Paragraph 13, A semiconductor memory device in which the above representative temperature value is the median of the above plane temperature values.
16. In Paragraph 13, A semiconductor memory device in which the above representative temperature value is the value obtained by multiplying a reference temperature value, which is the average or median value of the above plane temperature values, and a temperature weighting factor.
17. In Paragraph 16, A semiconductor memory device in which the above temperature weight is calculated based on the magnitude of a sum vector formed by summing multiple vectors, each directed toward each of the multiple temperature sensors, with the temperature center of the multiple temperature sensors as the origin.
18. In Paragraph 17, A semiconductor memory device in which each of the above plurality of vectors has a direction from the temperature center toward the corresponding temperature sensor and a magnitude of the plane temperature value obtained from the corresponding temperature sensor.
19. Multiple planes, each comprising multiple memory cells; A plurality of temperature sensors arranged corresponding to the plurality of planes above; A temperature compensation circuit that generates a lead determination voltage for performing a lead operation of the plurality of planes based on plane temperature values obtained from the plurality of temperature sensors; and A semiconductor memory device comprising a page buffer circuit that determines data by comparing the voltage level of a signal transmitted through bit lines connected to the plurality of planes with the read determination voltage.
20. Multiple planes, each comprising multiple memory cells; A plurality of temperature sensors arranged corresponding to the plurality of planes above; A temperature compensation circuit that generates a voltage control signal for controlling the level of shift control voltages to shift the threshold voltage distribution of the memory cells based on plane temperature values obtained from the plurality of temperature sensors; and A semiconductor memory device comprising a voltage generator that generates the shift control voltage based on the above voltage control signal.

Description

Semiconductor Memory Device The present disclosure relates to a semiconductor memory device for storing data. A semiconductor memory device may include a plurality of memory cells that store data. Additionally, semiconductor memory devices may be classified into nonvolatile memory devices that can retain stored data even when the power supply is interrupted, and volatile memory devices that cannot retain data when the power supply is interrupted. Memory cells included in a non-volatile memory device may vary in operating characteristics depending on the operating environment, such as temperature and/or the number of program/erase cycles. To prevent performance degradation of the non-volatile memory device caused by these variations in operating characteristics, it is necessary to provide the memory cells with an operating voltage corresponding to the temperature and/or the number of program/erase cycles. FIG. 1 is a block diagram showing a memory system according to an exemplary embodiment of the present disclosure. Figure 2 is a block diagram showing the memory device illustrated in Figure 1. Figure 3 shows an example of the arrangement of temperature sensors illustrated in Figure 2. FIG. 4 is a flowchart illustrating a temperature compensation method for a memory device according to one embodiment of the present disclosure. FIG. 5 is a diagram illustrating the operation according to step S430 of FIG. 4. Figure 6 is a diagram illustrating the operation according to step S440 of Figure 4. FIG. 7 is a flowchart illustrating a temperature compensation method for a memory device according to another embodiment of the present disclosure. FIG. 8 is a diagram illustrating an example of an operation according to step S720 of FIG. 7. Figure 9 is a diagram illustrating an example of a method for calculating a representative temperature value described in Figure 8. Various embodiments will be described below with reference to the attached drawings. However, the present disclosure is not limited to specific embodiments and should be understood to include various modifications, equivalents, and/or alternatives of the embodiments. Embodiments of the present disclosure may provide various effects that can be recognized directly or indirectly through the present disclosure. FIG. 1 is a block diagram showing a memory system according to an exemplary embodiment of the present disclosure. Referring to FIG. 1, a memory system (1) may include a memory device (10) and a memory controller (20). The memory system (1) can be implemented as internal memory embedded in an electronic system (e.g., smartphone, tablet PC, computer, TV, etc.). For example, the memory system (1) may be an embedded UFS (Universal Flash Storage), eMMC (embedded Multi-Media Card), or SSD (Solid State Drive). According to one embodiment, the memory system (1) may be implemented as external memory that is detachable from the electronic device, and may be, for example, a UFS memory card, CF (Compact Flash), SD (Secure Digital), Micro-SD (Micro Secure Digital), Mini-SD (Mini Secure Digital), xD (Extreme Digital), or Memory Stick. The memory system (1) can store data received from the host in the memory device (10) based on an access request from the host, or read data requested by the host from the memory device (10) and transmit it to the host. A memory device (10) may include a plurality of memory cells, each of which stores data. According to one embodiment, each of the plurality of memory cells may be a non-volatile memory cell that retains stored data even when the supplied power is cut off. For example, when the memory cell is a non-volatile memory cell, the memory device (10) may be an EEPROM (Electrically Erasable Programmable Read-Only Memory), a flash memory, a PRAM (Phase Change Random Access Memory), a RRAM (Resistance Random Access Memory), an NFGM (Nano Floating Gate Memory), a PoRAM (Polymer Random Access Memory), a MRAM (Magnetic Random Access Memory), or a FRAM (Ferroelectric Random Access Memory), etc. In the following, embodiments of the present disclosure are described with the example of the case where the plurality of memory cells are NAND flash memory cells, but the technical concept of the present disclosure is not limited thereto. The memory device (10) can perform program, read, and/or erase operations under the control of the memory controller (20). The memory controller (20) may provide a control signal (CTRL), a command (CMD), and an address (ADDR) to the memory device (10). The control signal (CTRL) may include information necessary for the memory device (10) to perform an operation corresponding to the command (CMD) received from the memory controller (20). For example, the control signal (CTRL) may include information regarding sensing parameters necessary for the memory device (10) to read data from memory cells. The command (CMD) may indicate an operation that the memory device (10) must perform during a program, read, or erase