KR-20260062639-A - Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are disclosed. The disclosed semiconductor device comprises: a lower electrode; a channel provided on the lower electrode; a gate insulating layer provided on the channel; a gate electrode provided on the gate insulating layer; and an upper electrode provided on the gate electrode; wherein the lower electrode includes a doping region, and the doping region includes In (Indium) or Nb (Niobium), and the lower electrode, the channel, and the lower electrode may be spaced apart in a direction perpendicular to the lower electrode.

Inventors

• 정규호
• 김상욱
• 양지은

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20241029

Claims (20)

1. Lower electrode; A channel provided in the lower electrode above; A gate insulating layer provided in the above channel; A gate electrode provided in the gate insulating layer; and Includes an upper electrode provided on the gate electrode; and A semiconductor device wherein the lower electrode comprises a doping region, the doping region comprises at least one of In (Indium) and Nb (Niobium), and the lower electrode, the channel, and the lower electrode are spaced apart in a direction perpendicular to the lower electrode.
2. In paragraph 1, The above doping region is provided in a region adjacent to the channel, a semiconductor device.
3. In paragraph 1, A semiconductor device in which the atomic percentage of at least one of the In and Nb in the doping region is 10 at% or more and 30 at% or less.
4. In paragraph 1, A semiconductor device in which the percentage of at least one atom of In and Nb in the doping region is higher in the portion adjacent to the channel than in the portion adjacent to the bottom of the lower electrode.
5. In paragraph 1, A semiconductor device comprising a channel including a lower portion, a first vertical extension portion extending from one end of the lower portion, and a second vertical extension portion extending from the other end of the lower portion.
6. In paragraph 1, The above channel is a semiconductor device comprising at least one of In(indium), Zn(zinc), Sn(tin), Ga(gallium) and Hf(hafnium).
7. In paragraph 1, A semiconductor device comprising a channel selected from the group consisting of InGaZnO, ZnO, ZrInZnO , InZnO , InGaZnO₄, ZnSnO , In₂O₃ , Ga₂O₃ , HfInZnO, GaInZnO, HfO₂, SnO₂, WO₃ , TiO₂ , Ta₂O₅ , In₂O₃SnO₂, MgZnO , ZnSnO₃ , ZnSnO₄ , CdZnO, CuAlO₂, CuGaO₂ , Nb₂O₅, TiSrO₃ , ZIO₄ ( zinc indium oxide), IGO₄ (indium gallium oxide), and combinations thereof.
8. In paragraph 1, It includes a molded insulating material in which the above channel is provided, A semiconductor device in which the doping region comprises In, the lower electrode comprises W (tungsten), and the mold insulator comprises SiN (silicon nitride).
9. In Article 1, It includes a molded insulating material in which the above channel is provided, A semiconductor device in which the doping region comprises Nb, the lower electrode comprises Ti (titanium), and the mold insulator comprises SiN (silicon nitride).
10. In Article 1, It includes a molded insulating material in which the above channel is provided, The above channel contacts the mold insulator at the first and second stages in a direction parallel to the lower electrode, and A semiconductor device in which the doping region is provided from the first stage to the second stage in a direction parallel to the lower electrode.
11. Step of forming an oxide layer on the lower electrode; A step of heat-treating the oxide layer to form a doping region on the lower electrode; A step of removing the oxide layer by wet etching; The method includes the step of forming a channel on the doping region; A method for manufacturing a semiconductor device, wherein the oxide layer comprises at least one of In (Indium) and Nb (Niobium), and the doping region comprises at least one of In and Nb.
12. In Paragraph 11, A method for manufacturing a semiconductor device, wherein the doping region is provided in a region adjacent to the channel.
13. In Paragraph 11, A method for manufacturing a semiconductor device, wherein the doping region is provided in a direction perpendicular to the lower electrode, extending to a region having a certain height from the upper surface of the lower electrode.
14. In Paragraph 11, A method for manufacturing a semiconductor device, wherein the atomic percentage of at least one of the In and Nb in the doping region is 10 at% or more and 30 at% or less.
15. In Paragraph 11, A method for manufacturing a semiconductor device in which the percentage of at least one atom of In and Nb in the doping region is higher in the portion adjacent to the channel than in the portion adjacent to the bottom of the lower electrode.
16. In paragraph 1, A method for manufacturing a semiconductor device, wherein the above channel comprises at least one of In(indium), Zn(zinc), Sn(tin), Ga(gallium) and Hf(hafnium).
17. In Paragraph 11, A method for manufacturing a semiconductor device , wherein the channel comprises a material selected from the group consisting of InGaZnO, ZnO, ZrInZnO, InZnO , InGaZnO₄ , ZnSnO , In₂O₃ , Ga₂O₃ , HfInZnO, GaInZnO , HfO₂ , SnO₂, WO₃ , TiO₂ , Ta₂O₅ , In₂O₃SnO₂ , MgZnO, ZnSnO₃ , ZnSnO₄, CdZnO , CuAlO₂, CuGaO₂ , Nb₂O₅, TiSrO₃ , ZIO₄ (zinc indium oxide), IGO₄ (indium gallium oxide), and combinations thereof.
18. In Paragraph 11, The method further includes the step of providing a molded insulating material on which the above channel is provided, and A method for manufacturing a semiconductor device, wherein the doping region comprises In, the lower electrode comprises W (tungsten), and the mold insulator comprises SiN (silicon nitride).
19. In Article 11, The method further includes the step of providing a molded insulating material on which the above channel is provided, and A method for manufacturing a semiconductor device, wherein the doping region comprises Nb, the lower electrode comprises Ti (titanium), and the mold insulator comprises SiN (silicon nitride).
20. In Article 11, The method further includes the step of providing a molded insulating material on which the above channel is provided, and The above channel contacts the mold insulator at the first and second stages in a direction parallel to the lower electrode, and A method for manufacturing a semiconductor device, wherein the doping region is provided from the first stage to the second stage in a direction parallel to the lower electrode.

Description

Semiconductor device and method of manufacturing the same An exemplary embodiment relates to a semiconductor device having a doping region formed on a lower electrode and a method for manufacturing the same. Transistors are semiconductor devices that perform the role of electrical switching and are employed in various integrated circuits, including memory, driver ICs, and logic devices. As the integration density of integrated circuits increases, the space occupied by transistors is rapidly shrinking; therefore, research is underway to maintain performance while reducing the size of transistors. One of the critical components of a transistor is the gate electrode. When voltage is applied to the gate electrode, the adjacent channel opens the path for current, and conversely, blocks the current. The performance of a semiconductor depends on how effectively leakage current is reduced and managed at the gate electrode and channel. In a transistor, power efficiency increases as the contact area between the gate electrode, which controls current, and the channel increases. As semiconductor processes become more miniaturized, transistor sizes decrease, and the contact area between the gate electrode and the channel shrinks, leading to problems caused by the short channel effect. Examples include phenomena such as threshold voltage variation, carrier velocity saturation, and deterioration of the subthreshold characteristics. Accordingly, methods to overcome the short channel effect and effectively reduce the channel length are being sought. FIG. 1 is a drawing illustrating a semiconductor device according to an exemplary embodiment. FIG. 2 is a drawing illustrating a semiconductor device including a buffer according to another exemplary embodiment. FIG. 3 is a drawing illustrating a semiconductor device including a buffer according to another exemplary embodiment. FIG. 4 is a flowchart illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment. FIGS. 5 to 15 are drawings for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment. FIG. 16 is a drawing illustrating a memory device including a semiconductor device according to an exemplary embodiment. FIG. 17 is a schematic block diagram of a display driver integrated circuit (display driver IC: DDI) including a semiconductor element according to an exemplary embodiment and a display device having the DDI. FIG. 18 is a circuit diagram of a CMOS inverter including a semiconductor device according to an exemplary embodiment. FIG. 19 is a circuit diagram of a CMOS SRAM device including a semiconductor device according to an exemplary embodiment. FIG. 20 is a circuit diagram of a CMOS NAND circuit including a semiconductor device according to an exemplary embodiment. FIG. 21 is a block diagram of an electronic system including a semiconductor device according to an exemplary embodiment. FIG. 22 is a block diagram of an electronic system including a semiconductor device according to an exemplary embodiment. Hereinafter, semiconductor devices and manufacturing methods according to various embodiments will be described in detail with reference to the attached drawings. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience of explanation. Terms such as "first," "second," etc., may be used to describe various components, but the components should not be limited by these terms. The terms are used solely for the purpose of distinguishing one component from another. A singular expression includes a plural expression unless the context clearly indicates otherwise. Furthermore, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. Additionally, the size or thickness of each component in the drawings may be exaggerated for clarity of description. The use of the term "above" and similar descriptive terms may apply to both singular and plural forms. Unless there is an explicit statement that the steps constituting the method must be performed in the described order, they may be performed in a suitable order. Furthermore, the use of all exemplary terms (e.g., etc.) is merely intended to describe the technical concept in detail and, unless limited by the claims, such terms do not limit the scope of the rights. FIG. 1 is a drawing illustrating a semiconductor device according to an exemplary embodiment. Referring to FIG. 1, a semiconductor device (100) may include a lower electrode (120), a doping region (130), an oxide channel (140), a gate electrode (150), a gate insulating layer (160), an upper electrode (170) and/or a mold insulating material (180). The lower electrode (120) may include a metal material. The lower electrode (120) may include a