KR-20260062640-A - Vertical NAND flash memory device and method of fabricating thereof, and electronic apparatus including the vertical NAND flash memory device

Abstract

A vertical NAND flash memory device and a method for manufacturing the same, and an electronic device including the vertical NAND flash memory device are disclosed. The disclosed vertical NAND flash memory device includes a plurality of cell arrays each extending vertically on a substrate. Each cell array comprises: a channel layer; a charge trap layer provided on the channel layer and comprising an amorphous oxide; at least one insertion layer provided inside the charge trap layer; and a plurality of gate electrodes provided on the charge trap layer.

Inventors

• 허호석
• 이민현
• 현승담

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20241029

Claims (20)

1. In a vertical NAND flash memory device comprising a plurality of cell arrays each extending vertically to a substrate, Each of the above cell arrays is, Channel layer; A charge trap layer provided in the above channel layer and comprising an amorphous oxide; At least one insertion layer provided inside the charge trap layer; and A vertical NAND flash memory device comprising a plurality of gate electrodes provided in the charge trap layer.
2. In Article 1, The charge trap layer comprises a ternary oxide comprising AlO, HfO, TaO, ZrO, LaO, GaO, YO, BaO, ScO, WO, or TiO, or a combination thereof, in a vertical NAND flash memory device.
3. In Article 2, A vertical NAND flash memory device comprising a charge trap layer expressed as MAlO (where M is Hf, Ta, Zr, La, Ga, Y, Ba, Xc, W or Ti, Al is aluminum, and O is oxygen).
4. In Paragraph 3, A vertical NAND flash memory device in which the ratio of the content of M to the content of (M+Al) is 0.2 or greater.
5. In Article 4, A vertical NAND flash memory device in which the ratio of the content of M to the content of (M+Al) is 0.5 or greater.
6. In Article 1, A vertical NAND flash memory device having a charge trap layer thickness of 50 Å to 80 Å.
7. In Article 1, The above insertion layer is a vertical NAND flash memory device comprising at least one of SiO, SiN, AlN, and BN.
8. In Article 1, A vertical NAND flash memory device having an insertion layer thickness of 2 Å to 15 Å.
9. In Article 8, A vertical NAND flash memory device having an insertion layer thickness of 4 Å to 10 Å.
10. In Article 1, A tunneling dielectric layer provided between the channel layer and the charge trap layer; and A vertical NAND flash memory device further comprising a barrier dielectric layer provided between the charge trap layer and the plurality of gate electrodes.
11. In Article 1, A vertical NAND flash memory device having a plurality of gate electrodes formed with a channel hole extending vertically to the substrate, wherein the charge trap layer, the at least one insertion layer, and the channel layer are stacked on the inner wall of the channel hole.
12. In Article 11, A vertical NAND flash memory device wherein the plurality of gate electrodes are spaced apart from each other in a direction perpendicular to the substrate, and each gate electrode is arranged to surround the charge trap layer.
13. An electronic device comprising a vertical NAND flash memory element described in any one of claims 1 to 12.
14. A step of alternately stacking a plurality of gate electrodes and a plurality of interlayer insulating layers on a substrate; A step of forming a channel hole penetrating the plurality of gate electrodes and the plurality of interlayer insulating layers; A step of forming a charge trap layer containing an amorphous oxide on the inner wall of the channel hole; A step of forming an insertion layer inside the charge trap layer; A step of forming a channel layer in the charge trap layer; and The method includes the step of heat-treating the charge trap layer; and A method for manufacturing a vertical NAND flash memory device configured such that the insertion layer prevents crystallization of the ternary oxide constituting the charge trap layer during the heat treatment process of the charge trap layer.
15. In Article 14, The step of forming the charge trap layer and the insertion layer is, A step of forming a first charge trap layer on the inner wall of the channel hole; A step of forming the insertion layer in the first charge trap layer; and A method for manufacturing a vertical NAND flash memory device comprising the step of forming a second charge trap layer on the insertion layer.
16. In Article 14, A method for manufacturing a vertical NAND flash memory device comprising a charge trap layer comprising a ternary oxide represented as MAlO (wherein M is Hf, Ta, Zr, La, Ga, Y, Ba, Xc, W or Ti, Al is aluminum, and O is oxygen).
17. In Article 16, A method for manufacturing a vertical NAND flash memory device in which the ratio of the content of M to the content of (M+Al) is 0.2 or higher.
18. In Article 14, A method for manufacturing a vertical NAND flash memory device in which the thickness of the charge trap layer is 50 Å to 80 Å.
19. In Article 14, A method for manufacturing a vertical NAND flash memory device in which the insertion layer comprises at least one of SiO, SiN, AlN, and BN.
20. In Article 14, A method for manufacturing a vertical NAND flash memory device in which the thickness of the insertion layer is 2Å to 15Å.

Description

Vertical NAND flash memory device and method of fabricating thereof, and electronic apparatus including the vertical NAND flash memory device The present disclosure relates to a vertical NAND flash memory device and a method for manufacturing the same, and an electronic device including the vertical NAND flash memory device. As conventional hard disks are being replaced by SSDs (Solid State Drives), NAND flash memory devices, which are non-volatile memory devices, are becoming widely commercialized. Recently, due to miniaturization and high integration, vertical NAND flash memory devices are being developed in which multiple memory cells are stacked perpendicular to the substrate. In vertical NAND flash memory devices, charge transfer between memory cells may occur due to an increase in the number of stacked layers and a decrease in height of memory cells, and such charge transfer can deteriorate the charge retention characteristics of the memory cells. FIG. 1 schematically illustrates a cross-section of a vertical NAND flash memory device according to an exemplary embodiment. Figure 2 is a perspective view illustrating the cell string shown in Figure 1. Figure 3 is an equivalent circuit diagram of a vertical NAND flash memory device shown in Figure 1. Figure 4 is a cross-sectional view showing an enlarged view of part A of Figure 1. FIG. 5a illustrates a first charge trap layer composed of an amorphous high dielectric constant material. FIG. 5b illustrates a second charge trap layer composed of a crystalline high dielectric constant material. Figure 6 shows the experimental results of measuring the charge loss for the first and second charge trap layers shown in Figures 5a and 5b. Figure 7a schematically illustrates the electronic band structure for a SiN charge trap layer. Figure 7b illustrates the electronic band structure of an HfAlO charge trap layer with an internal SiO insertion layer. Figures 8a and 8b are TEM images taken of HfAlO (24 cycles) deposited on a Si substrate using an Atomic Layer Deposition (ALD) process and then heat-treated. Figures 9a and 9b are TEM images taken of SiO (25 cycles)/bottom HfAlO (18 cycles)/SiO (1 cycle)/top HfAlO (18 cycles) sequentially deposited on a Si substrate using an ALD process, followed by heat treatment. Figures 10a and 10b are TEM images taken of SiO (25 cycles)/bottom HfAlO (18 cycles)/SiO (2 cycles)/top HfAlO (18 cycles) sequentially deposited on a Si substrate using an ALD process, followed by heat treatment. Figures 11a and 11b are TEM images taken of SiO (25 cycles)/bottom HfAlO (18 cycles)/SiO (5 cycles)/top HfAlO (18 cycles)/SiO (25 cycles) sequentially deposited on a Si substrate using an ALD process, followed by heat treatment. FIG. 12 is a cross-sectional view illustrating another exemplary charge trap layer and insertion layer that can be applied to a vertical NAND flash memory device according to an exemplary embodiment. FIGS. 13a to 13g are drawings for explaining a method for manufacturing a vertical NAND flash memory device according to an exemplary embodiment. FIG. 14 is a schematic block diagram of a display driver integrated circuit (display driver IC; DDI) and a display device having the DDI according to an exemplary embodiment. FIG. 15 is a block diagram illustrating an electronic device according to an exemplary embodiment. FIG. 16 is a block diagram of an electronic device according to an exemplary embodiment. FIG. 17 is a conceptual diagram schematically showing a device architecture that can be applied to an electronic device according to an exemplary embodiment. FIG. 18 is a conceptual diagram schematically showing a device architecture that can be applied to an electronic device according to another exemplary embodiment. Hereinafter, exemplary embodiments will be described in detail with reference to the attached drawings. In the drawings below, the same reference numerals denote the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience of explanation. Meanwhile, the embodiments described below are merely illustrative, and various modifications are possible from these embodiments. In the following, terms designated as "upper" or "upper" may include not only those located directly above, below, to the left, or to the right in contact, but also those located above, below, to the left, or to the right without contact. Singular expressions include plural expressions unless the context clearly indicates otherwise. Furthermore, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. The use of the term “for the above” and similar descriptive terms may be in both singular and plural. Unless there is an explicit description of the order of the steps constituting the method, these steps may be performed in a suitable order and are not necessarily lim