KR-20260062673-A - Pattern inspection method and semiconductor device manufacturing method including the same

KR20260062673AKR 20260062673 AKR20260062673 AKR 20260062673AKR-20260062673-A

Abstract

The technical concept of the present disclosure provides a pattern inspection method comprising: a step of forming a stack by stacking a plurality of layers, and then removing at least a portion of the stack to form a pattern that includes the hole and extends in the vertical direction; a step of forming a sample by forming a conductive layer having an internal hole inside the hole; a step of acquiring an image of the sample; and a step of analyzing the image.

Inventors

천지성
김연휴
신택수
김민규
심성호
이성호

Assignees

삼성전자주식회사

Dates

Publication Date: 20260507
Application Date: 20241029

Claims (10)

A method for inspecting a pattern including a hole extending in a vertical direction, A step of forming a stack by stacking a plurality of layers, and then removing at least a portion of the stack to form a pattern that includes the hole and extends in the vertical direction; A step of fabricating a sample by forming a conductive layer having an internal hole inside the above hole; A step of acquiring an image of the above sample; and A pattern inspection method characterized by including the step of analyzing the above image.
In Article 1, A pattern inspection method characterized by the conductive layer covering the side wall of the hole.
In Article 1, The step of producing the above sample is, A pattern inspection method characterized by including removing at least a portion of the stack.
In Paragraph 3, Removing at least a portion of the above stack is, Remove the above stack in the above vertical direction, or Remove the above stack in a horizontal direction parallel to the main surface of the stack, or A pattern inspection method characterized by removing the stack in a diagonal direction that is not parallel to the horizontal direction and the vertical direction, respectively.
A method for inspecting a pattern including a hole extending in a vertical direction, A step of forming a stack by stacking a plurality of layers, and then removing at least a portion of the stack to form a pattern that includes the hole and extends in the vertical direction; A step of forming a conductive layer having an inner hole inside the above hole; A step of producing a sample by removing at least a portion of the stack above; A step of acquiring an image of the above sample; and The step of analyzing the above image; is included, The step of producing a sample by removing at least a portion of the stack above is, A pattern inspection method characterized by the conductive layer being exposed to the outside of the stack.
In Article 5, It includes removing at least a portion of the conductive layer, A pattern inspection method characterized in that the removal rate of the conductive layer is lower than the removal rate of the stack.
In Article 5, When removing the above stack in the above vertical direction, The step of analyzing the above image is, A pattern inspection method characterized by being performed based on at least one of the diameter of the pattern in the image, the critical dimension (CD) of the pattern, the pitch of the pattern, and the spacing distance of the pattern.
In Article 5, When removing the above stack in a horizontal direction parallel to the main surface of the stack, The step of analyzing the above image is, A pattern inspection method characterized by being performed based on at least one of the vertical depth of the pattern and the horizontal separation distance of the pattern.
Step of preparing the wafer; A step of performing a semiconductor process for forming a pattern on the wafer that extends in a vertical direction perpendicular to a horizontal direction parallel to the main surface of the wafer; A step of inspecting the wafer on which the semiconductor process has been performed; and The method includes the step of performing a subsequent semiconductor process on the wafer; The step of inspecting the wafer above is, A step of forming a stack by stacking a plurality of layers on the wafer, and then removing at least a portion of the stack to form a pattern extending in the vertical direction that includes a hole; A step of fabricating a sample (SP) by forming a conductive layer having an internal hole inside the above hole; A step of acquiring an image of the above sample; and A method for manufacturing a semiconductor device characterized by including the step of analyzing the above image.
In Article 9, The step of producing a sample by removing at least a portion of the stack above is, A method for manufacturing a semiconductor device characterized by being performed by at least one of photolithography, etching, and chemical mechanical polishing (CMP).

Description

Pattern inspection method and semiconductor device manufacturing method including the same The present disclosure relates to a pattern inspection method and a method for manufacturing a semiconductor device including the same, and more specifically, to a pattern inspection method using an image and a method for manufacturing a semiconductor device including the same. As the integration density of semiconductor devices increases, semiconductor devices with vertical structures are being proposed instead of conventional semiconductor devices with planar structures. Semiconductor devices with vertical structures include structures that extend vertically on a substrate. However, as the integration density of semiconductor devices increases, the number of layers stacked vertically increases, and consequently, a precise inspection method for semiconductor devices is required. FIG. 1 is a flowchart illustrating a pattern inspection method according to one embodiment of the present disclosure. FIG. 2 is a drawing showing a pattern inspection device according to one embodiment of the present disclosure. FIG. 3 is a configuration diagram for explaining a scanning electron microscope (hereinafter SEM) according to one embodiment of the present disclosure. FIGS. 4 and FIGS. 5 are cross-sectional views illustrating a method for forming a pattern according to one embodiment of the present disclosure. FIG. 6 is a flowchart illustrating a method for producing a sample according to one embodiment of the present disclosure. FIG. 7 is a cross-sectional view illustrating a method for producing a sample according to one embodiment of the present disclosure. FIG. 8 is a plan view for explaining a method of producing a sample according to one embodiment of the present disclosure. FIG. 9 is a cross-sectional view showing the result of delayering being performed in a vertical direction on a stack according to one embodiment of the present disclosure. FIG. 10 is a cross-sectional view showing the result of delayering being performed horizontally on a stack according to one embodiment of the present disclosure. FIG. 11 is a cross-sectional view showing the result of delayering in a diagonal direction on a stack according to one embodiment of the present disclosure. FIGS. 12 and 13 are drawings for explaining the effect when a conductive layer according to one embodiment of the present disclosure is exposed outside of a sample. FIG. 14 is a schematic block diagram of a pattern inspection device according to one embodiment of the present disclosure. FIG. 15 is a flowchart illustrating a method for manufacturing a semiconductor device including a pattern inspection method according to one embodiment of the present disclosure. FIGS. 16 and FIGS. 17 are cross-sectional views for illustrating a subsequent process for a semiconductor device according to one embodiment of the present disclosure. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted. In the drawings below, the thickness or size of each layer is exaggerated for convenience and clarity of explanation, and accordingly, may differ somewhat from the actual shape and proportions. Terms indicating spatial position, such as "bottom," "below," "lower," "top," "upper," etc., used herein are intended solely for ease of understanding and are intended to describe the relative positional relationships between elements or patterns depicted in the drawings; they do not limit the technical scope of this disclosure in any sense. Terms regarding relative spatial position are intended to encompass variations in the orientation of the semiconductor device in addition to the directions disclosed in the drawings. That is, the semiconductor device may be oriented in various directions during use (or manufacturing), and even in such cases, the terms regarding position used herein will be readily understood by those skilled in the art. FIG. 1 is a flowchart illustrating a pattern inspection method according to one embodiment of the present disclosure. FIG. 2 is a drawing illustrating a pattern inspection device according to one embodiment of the present disclosure. Referring to FIGS. 1 and FIGS. 2, a pattern may first be formed (S100). In one embodiment, the pattern inspection method of the present disclosure may inspect a pattern of a semiconductor device. For example, the pattern inspection method of the present disclosure may inspect a pattern of a hole structure of a semiconductor device. For example, the pattern inspection method of the present disclosure may inspect a pattern of a memory semiconductor device. In one embodiment, the pattern inspection method of the present disclosure can inspect a pattern in which the cross-section of the pattern is polygonal, circular, elliptical, and/or irregular. As