KR-20260062686-A - METHOD OF ALIGNING SEMICONDUCTOR WAFER IN SCANNER DEVICE

Abstract

In a semiconductor wafer alignment method according to one embodiment of the present disclosure, a first mark pair comprises two marks among a plurality of marks of a semiconductor wafer. A plurality of mark pairs including the first mark pair are established by performing a geometric transformation one or more times on the first mark pair. A plurality of coarse model parameters are generated by performing a coarse wafer alignment (COWA) based on each of the plurality of mark pairs. A fine model parameter is generated by performing a fine wafer alignment (FIWA) based on the plurality of marks. Whether the alignment of the semiconductor wafer is successful is determined based on the plurality of coarse model parameters and the fine model parameter. A subsequent process is performed based on the determination that the alignment of the semiconductor wafer is successful.

Inventors

• 정우용
• 이승윤
• 이헌주
• 황찬

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20241029

Claims (10)

1. A step of setting a plurality of mark pairs including the first mark pair by performing a geometric transformation one or more times on a first mark pair including two marks among a plurality of marks of a semiconductor wafer; A step of generating multiple coarse model parameters by performing COWA (coarse wafer alignment) based on each of the above multiple pairs of marks; A step of generating fine model parameters by performing FIWA (fine wafer alignment) based on the above plurality of marks; A step of determining whether the alignment of the semiconductor wafer is successful based on the plurality of coarser model parameters and the fine model parameters; and A semiconductor wafer alignment method comprising the step of performing a subsequent process based on the judgment that the alignment of the semiconductor wafer is successful.
2. In claim 1, the step of setting the plurality of mark pairs is, A step of generating the first pair of marks by selecting two marks arranged at equal distances from the center of the semiconductor wafer; A step of generating a second pair of marks by performing a rotational transformation once on the first pair of marks based on the center of the semiconductor wafer; and A semiconductor wafer alignment method comprising the step of generating a plurality of mark pairs including the first mark pair and the second mark pair.
3. In claim 2, the step of setting the plurality of mark pairs is, A step of generating a third pair of marks by performing the rotation transformation once on the second pair of marks; and A semiconductor wafer alignment method further comprising the step of generating a plurality of mark pairs including the first mark pair, the second mark pair, and the third mark pair.
4. In Paragraph 3, A semiconductor wafer alignment method in which the rotation angle according to the rotation transformation for the first pair of marks is substantially the same as the rotation angle according to the rotation transformation for the second pair of marks.
5. In Article 2, The number of the above plurality of mark pairs is N (N is an integer greater than or equal to 2), and A semiconductor wafer alignment method in which the rotation angle according to the rotational transformation for the first pair of marks is (360/N) degrees.
6. In claim 1, the step of setting the plurality of mark pairs is, A step of generating a second pair of marks by performing a proportional transformation once on the first pair of marks; and A semiconductor wafer alignment method comprising the step of generating a plurality of mark pairs including the first mark pair and the second mark pair.
7. In claim 6, the step of setting the plurality of mark pairs is, A step of generating a third pair of marks by performing the proportional transformation once on the second pair of marks; and A semiconductor wafer alignment method further comprising the step of generating a plurality of mark pairs including the first mark pair, the second mark pair, and the third mark pair.
8. In claim 1, each of the plurality of coars model parameters is, A semiconductor wafer alignment method including model values related to wafer magnification, wafer rotation, non-orthogonality, and wafer translation.
9. A step of setting a plurality of mark pairs including the first mark pair by performing a geometric transformation one or more times on a first mark pair including two marks among a plurality of marks of a semiconductor wafer; A step of generating a plurality of model parameters by performing COWA and FIWA based on the plurality of mark pairs and the plurality of marks; A step of determining whether the alignment of the semiconductor wafer is successful based on the plurality of model parameters above; and A semiconductor wafer alignment method comprising the step of performing a subsequent process based on the judgment that the alignment of the semiconductor wafer is successful.
10. A step of setting a second pair of marks by performing a rotational transformation or a proportional transformation one or more times on a first pair of marks comprising two marks among a plurality of marks of a semiconductor wafer; A step of generating first coarser model parameters by performing COWA based on the first pair of marks above; A step of generating fine model parameters by performing FIWA based on the above plurality of marks; A step of determining whether the alignment of the semiconductor wafer is successful based on the first coarser model parameter and the fine model parameter; A step of generating second coarser model parameters by performing COWA based on the second mark pair based on the judgment that the alignment of the semiconductor wafer is not successful; and A semiconductor wafer alignment method comprising the step of determining whether the alignment of the semiconductor wafer is successful based on the second coarser model parameter and the fine model parameter.

Description

Method of Aligning Semiconductor Wafer in Scanner Device The present disclosure relates to a semiconductor device, and more specifically, to a semiconductor wafer alignment method for a scanner device. In a photolithography process for manufacturing semiconductor devices, a specific pattern can be formed on a semiconductor wafer coated with photoresist by irradiating it with light through a mask or reticle. In such photolithography processes, semiconductor wafer alignment must be performed prior to precisely form specific patterns on the wafer. As semiconductor processes become more miniaturized, the importance of semiconductor wafer alignment is increasing to manufacture high-quality semiconductors. FIG. 1 is a block diagram showing a photolithography facility including a scanner device for performing a semiconductor wafer alignment method according to one embodiment of the present disclosure. Figure 2 is a drawing for explaining the semiconductor wafer of Figure 1. FIG. 3 is a flowchart illustrating a semiconductor wafer alignment method according to one embodiment of the present disclosure. Figure 4 is a drawing for explaining the multiple marks of Figure 3. FIG. 5 is a block diagram showing one embodiment of the alignment unit of FIG. 1. FIG. 6 is a block diagram showing one embodiment of the alignment simulator of FIG. 5. FIG. 7 is a flowchart illustrating an example of the operation of the mark generator of FIG. 6. FIG. 8 is a drawing for explaining one embodiment of the first pair of marks of FIG. 3. FIG. 9 is a diagram illustrating an example of the geometric transformation of FIG. 3. FIG. 10 is a drawing for explaining one embodiment of the plurality of mark pairs of FIG. 3. FIG. 11 is a diagram illustrating an example of a plurality of coarser model parameters and fine model parameters of FIG. 3. FIG. 12 is a flowchart illustrating an example of the operation of the alignment verifier of FIG. 5. FIGS. 13a, FIGS. 13b, and FIGS. 13c are drawings for explaining the process of determining whether the alignment of a semiconductor wafer is successful. FIG. 14 is a flowchart illustrating a semiconductor wafer alignment method according to one embodiment of the present disclosure. FIG. 15 is a flowchart illustrating a semiconductor wafer alignment method according to one embodiment of the present disclosure. In the following, embodiments of the present disclosure will be described clearly and in detail so that a person skilled in the art can easily practice the present disclosure. FIG. 1 is a block diagram showing a photolithography facility including a scanner device for performing a semiconductor wafer alignment method according to one embodiment of the present disclosure. Referring to FIG. 1, photolithography equipment (10) may include a scanner device (100). The scanner device (100) may include an alignment unit (110) and an exposure unit (130). The alignment unit (110) may include an alignment simulator (111) and an alignment verifier (113). The alignment unit (110) performs alignment on a semiconductor wafer (1) delivered from the outside and can provide the semiconductor wafer (1) to an exposure unit (130) based on the judgment that the alignment is successful. The alignment can be performed by an alignment simulator (111), and the judgment that the alignment is successful can be performed by an alignment verifier (113). The exposure unit (130) can perform an exposure process on a semiconductor wafer (1) transferred from the alignment unit (110) and provide the semiconductor wafer (1) on which the exposure process has been performed to the outside. In one embodiment, the photolithography equipment (10) may further include a loading/unloading unit (11), a spinner device (13), and an interface unit (15). The loading/unloading unit (11) can load or unload a cassette loaded with a semiconductor wafer (1), and when the cassette is loaded, it can provide the loaded semiconductor wafer (1) to the spinner device (13). The spinner device (13) can perform a coating process and a baking process on the semiconductor wafer (1) delivered from the loading/unloading unit (11), and can provide the semiconductor wafer (1), on which the coating of photoresist and baking are completed, to the scanner device (100) through the interface unit (15). The spinner device (13) can perform a development process on the semiconductor wafer (1) delivered from the scanner device (100) through the interface unit (15), and can provide the developed semiconductor wafer (1) to the loading/unloading unit (11). The alignment of the semiconductor wafer (1) by the alignment unit (110) must be successful before the exposure process by the exposure unit (130) is performed. If the alignment of the semiconductor wafer (1) is not successful, the progress to the exposure process is stopped, and since subsequent processes after the alignment cannot proceed, the semiconductor wafer (1) in this case is discarded. A semiconductor wafer (1) may incl