KR-20260062689-A - SEMICONDUCTOR DEVICE

Abstract

The present disclosure relates to a semiconductor device, wherein a semiconductor device according to one embodiment may include a substrate comprising a first surface and a second surface facing each other, and a first device region and a second device region having different types of devices located thereon; a first channel pattern and a second channel pattern located on the first surface of the substrate in the first device region and the second device region, respectively; an insulating structure extending in a first direction between the first device region and the second device region; gate structures extending in a second direction intersecting the first direction, each surrounding the first channel pattern and the second channel pattern; source/drain patterns connected to both sides of the first channel pattern and the second channel pattern, respectively; a lower wiring located on the second surface of the substrate and connected to at least some of the source/drain patterns and a gate structure located at one edge of the first device region; and a device isolation film penetrating the gate structure located at the other edge of the first device region.

Inventors

• 김재인
• 박판제
• 박지수
• 김병성

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20241029

Claims (10)

1. A substrate comprising a first surface and a second surface facing each other, and a first element region and a second element region where different types of elements are located. A first channel pattern and a second channel pattern located on the first surface of the substrate, respectively, in the first element region and the second element region, An insulating structure extending in a first direction between the first element region and the second element region, Gate structures that surround the first channel pattern and the second channel pattern, respectively, and extend in a second direction intersecting the first direction, Source/drain patterns connected to both sides of the first channel pattern and the second channel pattern, A lower wiring located on a second surface of the substrate and connected to a gate structure located at least some of the source/drain patterns and one edge of the first element region, and A semiconductor device comprising a device isolation film penetrating a gate structure located at the other edge of the first device region.
2. In paragraph 1, A semiconductor device in which one side of the insulating structure contacts the first channel pattern in the second direction, and the other side of the insulating structure contacts the second channel pattern in the second direction.
3. In paragraph 1, A semiconductor device having a p-type element located in the first element region and an n-type element located in the second element region.
4. In paragraph 3, A semiconductor device wherein the second element region does not include the element isolation layer and includes gate structures located at both edges of the second element region and lower gate patterns connecting the lower wiring.
5. In paragraph 1, A p-type element is located in the first element region, and The above lower wiring is, A first lower wiring to which a first voltage is applied, and It includes a second lower wiring to which a second voltage lower than the first voltage is applied, and A semiconductor device comprising a first element region including a lower gate pattern connecting a gate structure located at one edge of the first element region and a first lower wiring.
6. In paragraph 1, An n-type element is located in the above-mentioned first element region, and The above lower wiring is A first lower wiring to which a first voltage is applied, and It includes a second lower wiring to which a second voltage lower than the first voltage is applied, and A semiconductor device comprising a first element region including a lower gate pattern connecting the gate structure located at one edge of the first element region and the second lower wiring.
7. In paragraph 1, It further includes gate separation structures spaced apart from the first channel pattern and the second channel pattern in the second direction, and Some of the above gate isolation structures face the insulating structure with the first channel pattern in between, Some of the above gate isolation structures are semiconductor devices facing the insulating structure with the above second channel pattern in between.
8. A substrate comprising a first surface and a second surface facing each other, and a first element region and a second element region where different types of elements are located. A first channel pattern and a second channel pattern located on the first surface of the substrate, respectively, in the first element region and the second element region, Insulating structures extending in a first direction with the first channel pattern and the second channel pattern in between, and facing in a second direction intersecting the first direction, Gate structures extending in the second direction, each surrounding the first channel pattern and the second channel pattern, Source/drain patterns connected to both sides of the first channel pattern and the second channel pattern, A lower wiring located on a second surface of the substrate and connected to a gate structure located at least some of the source/drain patterns and one edge of the first element region, and A semiconductor device comprising a device isolation film penetrating a gate structure located at the other edge of the first device region.
9. In paragraph 8, The above insulating structures are each semiconductor devices in contact with the first channel pattern and the second channel pattern in the second direction.
10. A substrate comprising a first surface and a second surface facing each other, and a first element region and a second element region where different types of elements are located. A first channel pattern and a second channel pattern located on the first surface of the substrate, respectively, in the first element region and the second element region, At least one insulating structure extending in a first direction and positioned adjacent to at least one of the first channel pattern or the second channel pattern in a second direction intersecting the first direction, Gate structures extending in the second direction, each surrounding the first channel pattern and the second channel pattern, Source/drain patterns connected to both sides of the first channel pattern and the second channel pattern, A semiconductor device comprising a lower wiring located on a second surface of the substrate, connected to at least some of the source/drain patterns, and connected to gate structures located at both edges of the first element region and the second element region.

Description

Semiconductor Device The present disclosure relates to a semiconductor device. A standard cell is a widely used design method in integrated circuit (IC) design, referring to a form in which small, repeatable transistor blocks are arranged in a predefined manner. Designs utilizing such standard cells can reduce design complexity, improve productivity, and guarantee a certain level of performance and power efficiency. However, as semiconductor process technology becomes miniaturized, issues such as interference between transistors and inefficient power consumption may arise; in particular, leakage current problems in the diffusion region negatively impact the performance of the integrated circuit. Diffusion Break is a technology designed to address leakage current issues. By isolating the diffusion region, it blocks unnecessary current flow, reduces power consumption, and mitigates electrical interference between transistors. This technology is primarily applied to the boundary between the P-type and N-type regions of a transistor to prevent continuous connection of diffusion layers. This prevents device performance degradation and improves power efficiency. Diffusion breakers play a particularly important role in high-density integrated circuits. This is because as the process becomes miniaturized, the distance between transistors decreases, increasing the potential for current leakage. Therefore, diffusion break technology has established itself as an essential element in the latest process technologies and is recognized as a critical component in high-performance, low-power semiconductor designs. FIGS. 1 and FIGS. 2 are layout drawings showing a semiconductor device according to one embodiment of the present disclosure. Figure 3 is a cross-sectional view of a semiconductor device along the AA' line of Figures 1 and 2. Figure 4 is a cross-sectional view of a semiconductor device along the BB' line of Figures 1 and 2. Figure 5 is a cross-sectional view of a semiconductor device along the CC' line of Figures 1 and 2. Figure 6 is a cross-sectional view of a semiconductor device along the DD' line of Figures 1 and 2. FIGS. 7 and FIGS. 8 are layout drawings showing a semiconductor device according to one embodiment of the present disclosure. Figure 9 is a cross-sectional view of a semiconductor device along the EE' line of Figures 7 and 8. FIG. 10 is a cross-sectional view of a semiconductor device along the FF' line of FIG. 7 and FIG. 8. FIGS. 11 and FIGS. 12 are layout drawings showing a semiconductor device according to one embodiment of the present disclosure. FIG. 13 is a cross-sectional view of a semiconductor device along the GG' line of FIG. 11 and FIG. 12. FIG. 14 is a cross-sectional view of a semiconductor device along the HH' line of FIG. 11 and FIG. 12. FIGS. 15 and 16 are layout drawings showing a semiconductor device according to one embodiment of the present disclosure. FIG. 17 is a cross-sectional view of a semiconductor device along line II' of FIG. 15 and FIG. 16. FIG. 18 is a cross-sectional view of a semiconductor device along the JJ' line of FIG. 15 and FIG. 16. FIGS. 19 and FIGS. 20 are layout drawings showing a semiconductor device according to one embodiment of the present disclosure. FIG. 21 is a cross-sectional view of a semiconductor device along the AA' line of FIG. 19 and FIG. 20. FIG. 22 is a cross-sectional view of a semiconductor device along the BB' line of FIG. 19 and FIG. 20. FIG. 23 is a cross-sectional view of a semiconductor device along the CC' line of FIG. 19 and FIG. 20. FIG. 24 is a cross-sectional view of a semiconductor device along the DD' line of FIG. 19 and FIG. 20. FIGS. 25 and 26 are layout drawings showing a semiconductor device according to one embodiment of the present disclosure. FIG. 27 is a cross-sectional view of a semiconductor device along the EE' line of FIG. 25 and FIG. 26. FIG. 28 is a cross-sectional view of a semiconductor device along the FF' line of FIG. 25 and FIG. 26. FIGS. 29 and FIGS. 30 are layout drawings showing a semiconductor device according to one embodiment of the present disclosure. FIG. 31 is a cross-sectional view of a semiconductor device along the GG' line of FIG. 29 and FIG. 30. FIG. 32 is a cross-sectional view of a semiconductor device along the HH' line of FIG. 29 and FIG. 30. FIGS. 33 and FIGS. 34 are layout drawings showing a semiconductor device according to one embodiment of the present disclosure. FIG. 35 is a cross-sectional view of a semiconductor device along line II' of FIG. 33 and FIG. 34. FIG. 36 is a cross-sectional view of a semiconductor device along the JJ' line of FIG. 33 and FIG. 34. Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein. To clear