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KR-20260062699-A - MEMORY DEVICE FOR FORMING OPTIMAL REFERENCE RESISTANCE FOR READ OPERATION OF OTP CELL ARRAY INCLUDING MAGNETIC TUNNEL JUNCTION DEVICES

KR20260062699AKR 20260062699 AKR20260062699 AKR 20260062699AKR-20260062699-A

Abstract

A memory cell array according to an embodiment of the present invention includes a main cell array configured to support a plurality of write operations and read operations, an OTP (One Time Programmable) cell array configured to support a single write operation and a plurality of read operations; and an OTP test cell array configured to form an Optimal Reference Resistance for a read operation of the OTP cell array, wherein each of the main cell array, the OTP cell array, and the OTP test cell array includes a plurality of memory cells each comprising a Magnetic Tunnel Junction (MTJ) element.

Inventors

  • 김대식

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260507
Application Date
20241029

Claims (10)

  1. A main cell array configured to perform multiple write operations and multiple read operations; One Time Programmable (OTP) cell array configured to perform one write operation and multiple read operations; and It includes an OTP test cell array configured to form an optimal reference resistance for a read operation of the above OTP cell array, and Each of the above main cell array, the above OTP cell array, and the above OTP test cell array includes a plurality of memory cells each comprising a magnetic tunnel junction (MTJ) element, and A plurality of memory cells of the above main cell array have resistance values corresponding to either a parallel state or an anti-parallel state, and A plurality of memory cells of the above OTP cell array and the above OTP test cell array are memory cell arrays having a resistance value corresponding to one of the breakdown state, the equilibrium state, or the above anti-equilibrium state.
  2. In Article 1, The above OTP test cell array is, It is further configured to record a check board pattern, which is a pattern in which the above yield state and the above equilibrium state appear alternately, in a plurality of memory cells included in the OTP test cell array, and A memory cell array in which the resistance value of the memory cell in the above breakdown state is smaller than the resistance value of the memory cell in the above equilibrium state.
  3. In Article 2, The above breakdown state is formed by applying a first voltage to the MTJ element to cause breakdown, and The above equilibrium state is formed by applying a second voltage to the MTJ element, and A memory cell array in which the first voltage is a voltage relatively larger than the second voltage.
  4. In Article 2, The above OTP test cell array is, Based on the change in resistance of the variable resistor, count the fail bits of the plurality of memory cells on which the check board pattern is recorded, and A memory cell array further configured to calculate the optimal reference resistance based on the counted fail bits.
  5. In Paragraph 4, A memory cell array in which the above optimal reference resistance is greater than the resistance value of the breakdown state and smaller than the resistance value of the equilibrium state.
  6. A first memory cell array; and It includes a second memory cell array, The above first memory cell array is, It includes a main cell array configured to support multiple write and read operations, and The above second memory cell array is, One Time Programmable (OTP) cell array configured to support one write operation and multiple read operations; and It includes an OTP test cell array configured to form an optimal reference resistance for a read operation of the above OTP cell array, and Each of the above main cell array, the above OTP cell array, and the above OTP test cell array includes a plurality of memory cells each comprising a magnetic tunnel junction (MTJ) element, and A plurality of memory cells of the above main cell array have resistance values corresponding to either a parallel state or an anti-parallel state, and A plurality of memory cells of the above OTP cell array and the above OTP test cell array are memory cell arrays having a resistance value corresponding to one of the breakdown state, the equilibrium state, or the above anti-equilibrium state.
  7. In Article 6, The above OTP test cell array is, It is further configured to record a check board pattern, which is a pattern in which the above yield state and the above equilibrium state appear alternately, in a plurality of memory cells included in the OTP test cell array, and A memory cell array in which the resistance value of the memory cell in the above breakdown state is smaller than the resistance value of the memory cell in the above equilibrium state.
  8. In Article 7, The above breakdown state is formed by applying a first voltage to the MTJ element to cause breakdown, and The above equilibrium state is formed by applying a second voltage to the MTJ element, and A memory cell array in which the first voltage is a voltage relatively larger than the second voltage.
  9. In Article 7, The above OTP test cell array is, Based on the change in resistance of the variable resistor, count the fail bits of the plurality of memory cells on which the check board pattern is recorded, and A memory cell array further configured to calculate the optimal reference resistance based on the counted fail bits.
  10. In Article 9, A memory cell array in which the above optimal reference resistance is greater than the resistance value of the breakdown state and smaller than the resistance value of the equilibrium state.

Description

Memory device for forming an optimal reference resistance for read operation of an OTP cell array including magnetic tunnel junction devices The present invention relates to a memory device, and more specifically, to a memory device that forms an optimal reference resistor for a read operation of an OTP cell array including MTJ elements. Recently, various types of electronic devices have been utilized. Consequently, driven by the demand for high speed and low power consumption in electronic devices, there is also a growing need for reliability, high speed, and low power consumption in memory devices included in electrical equipment. To meet these requirements, magnetic memory devices have been proposed as memory elements for such devices. Since magnetic memory devices possess characteristics such as high-speed operation and non-volatility, they are gaining attention as next-generation semiconductor memory devices. Generally, a magnetic memory device may include a magnetic tunnel junction (MTJ) device. An MTJ device may include two magnetic materials and an insulating film interposed between them. The resistance value of the MTJ device may vary depending on the magnetization directions of the two magnetic materials. For example, when the magnetization directions of the two magnetic materials are semi-equilibrium, the MTJ device may have a large resistance value, and when the magnetization directions of the two magnetic materials are equilibrium, the MTJ device may have a small resistance value. Data can be programmed and read using this difference in resistance values. FIG. 1 is a block diagram showing a memory device according to an embodiment of the present invention. FIG. 2 shows a memory cell array according to an embodiment of the present invention. FIG. 3a is a diagram showing the dispersion of resistance values of main memory cells according to an embodiment of the present invention. FIG. 3b is a diagram showing the dispersion of resistance values of OTP cells and OTP test cells according to an embodiment of the present invention. Figure 4 conceptually illustrates determining the value of the optimal reference resistance. Figure 5 is a flowchart showing the operation of a memory device. FIGS. 6A and FIGS. 6B show various embodiments of the memory cell array of FIG. 1. FIG. 7 shows a memory cell array according to an embodiment of the present invention. Figure 8 shows another embodiment of the memory device of Figure 1. Figure 9 illustrates an exemplary configuration of a variable resistor. In the following, embodiments of the present invention will be described clearly and in detail so that a person skilled in the art can easily practice the present invention. FIG. 1 is a block diagram showing a memory device according to an embodiment of the present invention. Referring to FIG. 1, the memory device (100) may include a memory cell array (110), a row decoder (120), a column decoder (130), a write driver (140), a sensing circuit (150), a source line driver (160), an input/output circuit (170), and a control logic circuit (180). In one embodiment, the memory device (100) may be a non-volatile memory device including non-volatile memory cells such as MRAM. For the purposes of easily describing embodiments of the present invention, the memory device (100) is assumed to be an MRAM device. However, the scope of the present invention is not limited thereto. A memory cell array (110) may include a main cell array (111), an OTP cell array (112), and an OTP test cell array (113). Each of the main cell array (111), the OTP cell array (112), and the OTP test cell array (113) may include a plurality of memory cells. Each of the plurality of memory cells may be connected to word lines (WL), bit lines (BL), and source lines (SL). The plurality of memory cells may be MRAM (Magnetic Random Access Memory) cells. For example, each of the plurality of memory cells may include a Magnetic Tunnel Junction (MTJ) element in which the value of the written data is determined according to the resistance value, but the scope of the present invention is not limited thereto. Data can be written to or read from the main cell array (111) by an external host device (not shown). For example, multiple memory cells included in the main cell array (111) may have a parallel state or an anti-parallel state, and data may be distinguished according to the state of the multiple memory cells. For example, the resistance value of a memory cell in a parallel state may be smaller than the resistance value of a memory cell in an anti-parallel state, and data may be distinguished based on the difference in resistance values. For example, a memory cell in a parallel state may be considered to store data of a first value (e.g., logic ‘0’). On the other hand, a memory cell in an anti-parallel state may be considered to store data of a second value (e.g., logic ‘1’). In one embodiment, the balanced state or semi-balanced state of a plurality of memory ce