KR-20260062825-A - SYSTEMS AND METHODS OF THERMAL DISSIPATION VIAS FOR STACKED MEMORY MODULES

Abstract

The systems and methods described herein include systems, methods, and apparatus for thermal dissipation vias for stacked memory modules. In some aspects, the technology described herein relates to an apparatus comprising: a first through-silicon via (TSV) for thermal dissipation routed vertically adjacently to at least one of a first memory stack or a second memory stack; and a second through-silicon via for thermal dissipation routed horizontally between a physical layer (PHY) of the first memory stack and a first memory die of the first memory stack, or between a physical layer of the second memory stack and at least one of a first memory die of the second memory stack.

Inventors

• 정현권

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20250903

Priority Date

20250411

Claims (20)

1. A first through-silicon via (TSV) for heat dissipation routed vertically adjacent to at least one of a first memory stack or a second memory stack; and A device comprising: a second through-silicon via for heat dissipation horizontally routed between at least one of the physical layer (PHY) of the first memory stack and the first memory die of the first memory stack, or the physical layer of the second memory stack and the first memory die of the second memory stack.
2. In Article 1, The first memory die of the first memory stack and the second memory die of the first memory stack, or Among the first memory die of the second memory stack and the second memory die of the second memory stack A device characterized by further comprising a third through-silicon via horizontally routed between at least one.
3. In Article 1, A device characterized in that the first through silicon via is connected to a first metal layer located on the first memory stack and the second memory stack.
4. In Paragraph 3, A device characterized by further including a heat sink located on the upper surface of the first metal layer.
5. In Article 1, A device characterized in that the first through silicon via is connected to a second metal layer below each of the first memory stack and the second memory stack.
6. In Article 5, A device characterized in that the second metal layer is located below at least one of the physical layer of the first memory stack or the physical layer of the second memory stack.
7. In Article 1, A device characterized in that the second through silicon via is connected to at least one of a first metal sidewall adjacent to the outer surface of the first memory stack or a second metal sidewall adjacent to the outer surface of the second memory stack.
8. In Article 7, A device characterized in that the first through silicon via is disposed between the inner surface of the first memory stack and the inner surface of the second memory stack.
9. In Article 1, An apparatus characterized in that at least one of the first through-silicon via or the second through-silicon via is routed through a semiconductor deposited on at least one of the first memory stack or the second memory stack.
10. In Article 1, A device characterized in that the second through-silicon via is connected to the first through-silicon via.
11. In Article 1, A first through-silicon via for heat dissipation routed vertically adjacent to at least one of the first die stack or the second die stack; and A stacked IC device comprising: a second through-silicon via for heat dissipation horizontally routed between at least one of the physical layer of the first die stack and the first IC die of the first die stack, or the physical layer of the second die stack and the first IC die of the second die stack.
12. In Article 11, The physical layer of the first stack and the first IC (integrated circuit) die of the first die stack and the second die of the first die stack, or among the first IC die of the second die stack and the second IC die of the second die stack A stacked IC device characterized by further including a third through-silicon via horizontally disposed between at least one.
13. In Article 11, A stacked IC device characterized in that the first silicon through-via is connected to a first metal layer located on the first die stack and the second die stack.
14. In Article 13, A stacked IC device characterized by further including a heat sink located on the upper surface of the first metal layer.
15. In Article 11, A stacked IC device characterized in that the first silicon through-via is connected to a second metal layer located below each of the first die stack and the second die stack.
16. In Article 15, A stacked IC device characterized in that the second metal layer is located below at least one of the physical layer of the first die stack or the physical layer of the second die stack.
17. In Article 11, A stacked IC device characterized in that the second silicon through-via is connected to at least one of a first metal sidewall adjacent to the outer surface of the first die stack or a second metal sidewall adjacent to the outer surface of the second die stack.
18. A step of routing a first through silicon via vertically adjacent to at least one of the first memory stack or the second memory stack for heat dissipation; and A heat dissipation method comprising the step of horizontally routing a second through silicon via between at least one of the physical layer of the first memory stack and the first memory die of the first memory stack, or between the physical layer of the second memory stack and the first memory die of the second memory stack, for heat dissipation.
19. In Article 18, The first memory die of the first memory stack and the second memory die of the first memory stack, or Among the first memory die of the second memory stack and the second memory die of the second memory stack A heat dissipation method characterized by further including the step of routing a third through silicon via horizontally routed between at least one.
20. In Article 18, A heat dissipation method characterized in that the first through silicon via is connected to a first metal layer located on top of each of the first memory stack and the second memory stack.

Description

Systems and methods of thermal dissipation vias for stacked memory modules The present disclosure generally relates to memory systems, and more specifically to thermal emission vias for stacked memory modules. <Cross-reference of related applications> This application claims priority to U.S. Provisional Application No. 63/713,557 filed with the U.S. Patent and Trademark Office on October 29, 2024, the contents of said application are incorporated herein by reference in their entirety. This background information is provided for context only, and the disclosure of any concept in this field of technology does not constitute an acknowledgment that such concept is prior art. Memory management is a form of resource management applied to computer memory. Some aspects of memory management dynamically allocate portions of memory in response to program requests and release the allocated memory for reuse when it is no longer needed. Memory management provides important functions to computer systems. However, improvements in memory management can be made in relation to high-performance computing and artificial intelligence (AI) systems. This disclosure generally relates to memory systems, in particular to thermal dissipation vias of stacked memory modules. The aforementioned aspects and other aspects of the system and method will be better understood when reading this application with reference to the drawings below, in which like numbers indicate similar or identical elements. Furthermore, the drawings provided herein are provided solely for the purpose of illustrating specific embodiments, and other embodiments not explicitly illustrated are not excluded from the scope of the invention. These features and advantages of the present invention and other features and advantages will be understood by referring to the specification, claims and attached drawings, wherein; FIG. 1 illustrates an exemplary system according to one or more embodiments described in this specification. FIG. 2 illustrates details of the system of FIG. 1 according to one or more embodiments described in this specification. FIG. 3 illustrates an exemplary system according to one or more embodiments described in this specification. FIG. 4 illustrates an exemplary system according to one or more embodiments described in this specification. FIG. 5 illustrates an exemplary system according to one or more embodiments described in this specification. FIG. 6 illustrates a flowchart illustrating an exemplary method related to a disclosed system according to an exemplary embodiment described in this specification. FIG. 7 illustrates a flowchart illustrating an exemplary method related to a disclosed system according to an exemplary embodiment described in this specification. Although the present system and method may be made in various modifications and alternative forms, specific embodiments thereof are illustrated by way of example in the drawings and will be described herein. The drawings may not be in scale. However, it should be understood that the drawings and the detailed description thereof are intended not to limit the present system and method to the specific form disclosed, but to encompass all modifications, equivalents, and alternatives within the spirit and scope of the present system and method as defined by the appended claims. Details of one or more embodiments of the invention described herein are provided in the accompanying drawings and the following description. Other features, aspects, and advantages of the invention will become apparent from the description, drawings, and claims of the invention. Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings, in which some embodiments are illustrated but not all. In practice, the present invention may be embodied in various forms and should not be interpreted as being limited to the embodiments presented herein. Rather, such embodiments are provided to satisfy applicable legal requirements. Unless otherwise specified, the term "or" is used in this specification in an alternative and conjunctive sense. The term "exemplary" is used as an example that does not indicate a level of quality. Identical numbers throughout the drawings indicate identical elements. Arrows in each drawing indicate bidirectional data flow and/or bidirectional data flow functions. In this document, the terms "path" and "route" are used interchangeably. Embodiments of the present disclosure may be implemented in various ways, including computer program products comprising manufactured products. Computer program products may include non-transient computer-readable storage media storing applications, programs, program components, scripts, source code, program code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, etc. (also referred to herein as executable instructions, instructions for execution, computer p