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KR-20260062844-A - SUBSTRATE AND MANUFACTURING METHOD FOR THE SAME

KR20260062844AKR 20260062844 AKR20260062844 AKR 20260062844AKR-20260062844-A

Abstract

A substrate according to an embodiment includes a glass core having an upper surface. The Rmax value, which is the maximum height roughness of the upper surface of the glass core, is 3 nm to 7 nm. The surface energy of the upper surface of the glass core is 50 mN/m to 63 mN/m. In this case, an insulating layer with improved peel resistance can be implemented on the glass core, and the electrical reliability of the substrate can be further improved.

Inventors

  • 김성진
  • 김진철

Assignees

  • 앱솔릭스 인코포레이티드

Dates

Publication Date
20260507
Application Date
20251021
Priority Date
20241029

Claims (18)

  1. It includes a glass core having an upper surface, and The Rmax value, which is the maximum height roughness of the upper surface of the glass core, is 3nm to 7nm, and A substrate having a surface energy of 50 mN/m to 63 mN/m on the upper surface of the glass core.
  2. In paragraph 1, A substrate in which the ratio of the contact angle of water on the upper surface of the glass core to the contact angle of diiodomethane on the upper surface of the glass core is 0.75 or higher.
  3. In paragraph 1, A substrate having a contact angle with water on the upper surface of the glass core of 40 to 55 degrees.
  4. In paragraph 1, A substrate having an arithmetic mean roughness Ra value of the upper surface of the glass core of 0.3 nm to 0.5 nm.
  5. In paragraph 1, A substrate having a square root mean roughness Rq value of the upper surface of the glass core of 0.4 nm to 1 nm.
  6. In paragraph 1, It further includes an insulating layer disposed on the above glass core, and The above insulating layer comprises an epoxy resin, and is a substrate.
  7. In paragraph 6, A substrate having a peel strength of the insulating layer on the upper surface of the glass core measured by a 90° peeling test of 25 N/ cm² or more.
  8. In paragraph 6, A substrate having a shear strength of the insulating layer on the upper surface of the glass core of 40 N/ cm² or more.
  9. In paragraph 1, The above substrate is a substrate having a semiconductor packaging application.
  10. In paragraph 1, It includes a first redistribution layer disposed on the above glass core, and The first redistribution layer comprises an electrically conductive layer and an insulating layer surrounding at least a portion of the electrically conductive layer, and The above-mentioned first redistribution layer includes an upper surface, and A substrate having a waviness of 0.7 μm or less on the upper surface of the first redistribution layer.
  11. In Paragraph 10, The above electrically conductive layer includes a first electrically conductive layer formed in contact with the upper surface of the glass core, and A substrate in which the ratio of the area occupied by the first electrically conductive layer on the upper surface of the glass core to the total area of the upper surface of the glass core is 80% or less.
  12. In Paragraph 11, A substrate having a thickness of 10㎛ to 50㎛ of the first electrically conductive layer.
  13. In Paragraph 10, A substrate having an elastic modulus of 8 GPa or less measured at 23°C of the insulating layer.
  14. In Paragraph 10, A substrate having a thermal expansion coefficient of the insulating layer of 60 ppm/℃ or less.
  15. In Paragraph 10, The above insulating layer includes a filler, and A substrate in which the insulating layer comprises 65 weight percent or more of the filler.
  16. In Paragraph 10, A substrate in which the ratio of the thickness of the first redistribution layer to the thickness of the glass core is 0.1 to 1.
  17. It includes a glass core and a first redistribution layer disposed on the glass core, and The first redistribution layer comprises an electrically conductive layer and an insulating layer surrounding at least a portion of the electrically conductive layer, and The above-mentioned first redistribution layer includes an upper surface, and A substrate having a waviness of 0.7 μm or less on the upper surface of the first redistribution layer.
  18. A preparatory stage for preparing a basic glass plate; and A substrate is manufactured by including a roughening step of providing a glass core formed by roughening the upper surface of the above-mentioned basic glass plate; and The above glass core has an upper surface, The Rmax value, which is the maximum height roughness of the upper surface of the glass core, is 3nm to 7nm, and A method for manufacturing a substrate in which the surface energy of the upper surface of the glass core is 50 mN/m to 63 mN/m.

Description

Substrate and Manufacturing Method for the Same An embodiment relates to a substrate and a method for manufacturing the same, etc. In the production of electronic components, implementing circuits on a semiconductor wafer is called the front-end process (FE), and assembling the wafer into a state usable in an actual product is called the back-end process (BE), and the packaging process is included in the back-end process. The four core technologies of the semiconductor industry that have enabled the rapid development of electronic products in recent years are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. While semiconductor technology is evolving into various forms, such as sub-micron and nano-scale linewidths, over ten million cells, high-speed operation, and significant heat dissipation, the technology to perfectly package these technologies has not yet been sufficiently supported. Consequently, the electrical performance of semiconductors is sometimes determined by packaging technology and the resulting electrical connections, rather than by the performance of the semiconductor technology itself. Ceramic or resin is used as the material for packaging substrates. In the case of ceramic substrates, it is difficult to mount high-performance, high-frequency semiconductor devices due to high resistance or dielectric constant. While resin substrates allow for the mounting of relatively high-performance, high-frequency semiconductor devices, there are limitations in reducing the wiring pitch. Recently, research is underway on applying silicon or glass as packaging substrates for high-end applications. By forming through-holes in silicon or glass substrates and applying conductive materials to these holes, the wiring length between the device and the motherboard can be shortened, and superior electrical characteristics can be achieved. FIG. 1 is a plan view illustrating a substrate according to one embodiment of the present specification. FIG. 2 is a plan view illustrating a substrate according to another embodiment of the present specification. FIG. 3 is a plan view illustrating a substrate according to another embodiment of the present specification. FIG. 4 is a plan view illustrating a substrate according to another embodiment of the present specification. Hereinafter, embodiments are described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. Throughout the specification, similar parts are denoted by the same reference numerals. Throughout this specification, the term “combination thereof” included in the Markush-type expression means one or more mixtures or combinations selected from the group consisting of the components described in the Markush-type expression, and means including one or more selected from the group consisting of said components. Throughout this specification, terms such as “first,” “second,” or “A,” “B” are used to distinguish identical terms from one another. Additionally, singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, the “~” system may mean that the compound contains a compound corresponding to “~” or a derivative of “~”. In this specification, the meaning that B is located on A means that B is located in direct contact with A or that B is located on A with another layer located between them, and is not interpreted as being limited to B being located in contact with the surface of A. In this specification, the meaning of being connected to B on A means that A and B are directly connected or connected through other components between A and B, and unless otherwise specifically stated, it is not interpreted as being limited to a direct connection between A and B. In this specification, singular expressions are interpreted to include singular or plural forms as interpreted in context unless otherwise specified. In this specification, the shapes, relative sizes, angles, etc., of each component in the drawings are exemplary and may be exaggerated for illustrative purposes, and the rights are not interpreted as being limited to the drawings. In this specification, "A and B are adjacent" means that A and B are located in contact with each other, or that A and B are located close to each other even if they are not in contact. Unless otherwise specified, the expression "A and B are adjacent" in this specification is not interpreted as being limited to A and B being in contact with each other. In this specification, the term "high frequency" means a frequency of about 1 GHz to about 300 GHz. Specifically, it may mean a frequency of about 1 GHz to about 30 GHz, and may mean a frequency of about 1 GHz to about 15 GHz. In this specification, the term