KR-20260062850-A - PACKAGING SUBSTRATE AND SEMICONDUCTOR PACKAGE COMPRISING THE SAME

Abstract

A packaging substrate according to an embodiment includes a core layer and an insulating layer disposed on the core layer. The insulating layer includes an insulating resin. The insulating layer includes a first insulating layer and a second insulating layer disposed on the first insulating layer. The hydroxyl group peak intensity measured by FT-IR of the second insulating layer is smaller than the hydroxyl group peak intensity measured by FT-IR of the first insulating layer. The moisture absorption amount of the packaging substrate measured after being left for 7 days in an atmosphere of 23°C and 50 RH% is 500 ppm to 1200 ppm. In such cases, it is possible to provide a packaging substrate, etc., in which long-term durability and electrical reliability are stably maintained.

Inventors

• 김성진
• 김진철

Assignees

• 앱솔릭스 인코포레이티드

Dates

Publication Date

20260507

Application Date

20251022

Priority Date

20241029

Claims (8)

1. It includes a core layer and an insulating layer disposed on the core layer, and The above insulating layer comprises an insulating resin, and The above insulating layer includes a first insulating layer and a second insulating layer disposed on the first insulating layer, and The hydroxyl group peak intensity measured by FT-IR of the second insulating layer is smaller than the hydroxyl group peak intensity measured by FT-IR of the first insulating layer, and A packaging substrate having a moisture absorption amount of 500 ppm to 1200 ppm measured after being left for 7 days in an atmosphere of 23℃ and 50 RH%.
2. In paragraph 1, A packaging substrate having an Rhd value, which is the hydroxyl group reduction rate of Equation 1 below, of 30% to 80%; [Equation 1] In the above Equation 1, H1 is the hydroxyl group peak intensity measured by FT-IR of the first insulating layer, and H2 is the hydroxyl group peak intensity measured by FT-IR of the second insulating layer.
3. In paragraph 1, A packaging substrate having an elastic modulus of 4 GPa to 8 GPa measured at 23°C of the insulating layer.
4. In paragraph 1, The insulating layer is disposed in contact with at least a portion of the upper surface of the core layer, and A packaging substrate in which the peel strength of the insulating layer on the upper surface of the core layer, measured by a 90° peeling test, is 25 N/ cm² or higher.
5. In paragraph 1, The insulating layer is disposed in contact with at least a portion of the upper surface of the core layer, and A packaging substrate having a shear strength of the insulating layer on the upper surface of the core layer of 40 N/ cm² or more.
6. In paragraph 1, The above insulating resin is a packaging substrate comprising an epoxy resin.
7. In paragraph 1, A packaging substrate in which the core layer is a glass core or a ceramic core.
8. A semiconductor package comprising a packaging substrate of claim 1 and a device electrically connected to said packaging substrate.

Description

Packaging substrate and semiconductor package comprising the same An embodiment relates to a packaging substrate and a semiconductor package including the same. In the production of electronic components, implementing circuits on a semiconductor wafer is called the front-end process (FE), and assembling the wafer into a state usable in an actual product is called the back-end process (BE), and the packaging process is included in the back-end process. The four core technologies of the semiconductor industry that have enabled the rapid development of electronic products in recent years are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. While semiconductor technology is evolving into various forms, such as sub-micron and nano-scale linewidths, over ten million cells, high-speed operation, and significant heat dissipation, the technology to perfectly package these technologies has not yet been sufficiently supported. Consequently, the electrical performance of semiconductors is sometimes determined by packaging technology and the resulting electrical connections, rather than by the performance of the semiconductor technology itself. Ceramic or resin is used as the material for packaging substrates. In the case of ceramic substrates, it is difficult to mount high-performance, high-frequency semiconductor devices due to high resistance or dielectric constant. While resin substrates allow for the mounting of relatively high-performance, high-frequency semiconductor devices, there are limitations in reducing the wiring pitch. Recently, research is underway on applying silicon or glass as packaging substrates for high-end applications. By forming through-holes in silicon or glass substrates and applying conductive materials to these holes, the wiring length between the device and the motherboard can be shortened, and superior electrical characteristics can be achieved. FIG. 1 is a cross-sectional view illustrating a packaging substrate according to one embodiment of the embodiment. FIG. 2 is a cross-sectional view illustrating a packaging substrate according to another embodiment of the embodiment. Hereinafter, embodiments are described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. Throughout the specification, similar parts are denoted by the same reference numerals. Throughout this specification, the term “combination thereof” included in the Markush-type expression means one or more mixtures or combinations selected from the group consisting of the components described in the Markush-type expression, and means including one or more selected from the group consisting of said components. Throughout this specification, terms such as “first,” “second,” or “A,” “B” are used to distinguish identical terms from one another. Additionally, singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, the “~” system may mean that the compound includes a compound corresponding to “~” or a compound derived from “~”. In this specification, the meaning that B is located on A means that B is located in direct contact with A or that B is located on A with another layer located between them, and is not interpreted as being limited to B being located in contact with the surface of A. In this specification, the meaning of being connected to B on A means that A and B are directly connected or connected through other components between A and B, and unless otherwise specifically stated, it is not interpreted as being limited to a direct connection between A and B. In this specification, singular expressions are interpreted to include singular or plural forms as interpreted in context unless otherwise specified. In this specification, the shapes, relative sizes, angles, etc., of each component in the drawings are exemplary and may be exaggerated for illustrative purposes, and the rights are not interpreted as being limited to the drawings. In this specification, "A and B are adjacent" means that A and B are located in contact with each other, or that A and B are located close to each other even if they are not in contact. Unless otherwise specified, the expression "A and B are adjacent" in this specification is not interpreted as being limited to A and B being in contact with each other. In this specification, the term "fine line" means a line having a width of 5 μm or less, unless otherwise described, and exemplarily means a line having a width of 1 to 4 μm or less. Unless otherwise specified in this specification, the physical property values of each component within the packaging substrate are interpreted as being measured at room temperature. Room temperature is 20°C to 25°C. In this specificati