KR-20260062852-A - MODULAR SEMICONDUCTOR SYSTEM AND METHOD OF MANUFACTURING THEREOF

Abstract

A semiconductor system according to the present invention comprises a plurality of components including a first component and a second component, wherein the first component includes first connection regions on a first surface and the second component includes second connection regions on a second surface, at least one of the first connection regions is connected to at least one of the second connection regions, and the first width in a first horizontal direction of the first component substantially corresponds to a first integer multiple of the first basic unit width in the first horizontal direction, and the first width in a first horizontal direction of the second component substantially corresponds to a second integer multiple of the first basic unit width, wherein the second integer multiple is different from the first integer multiple.

Inventors

• 마르티노 제이슨
• 리 얀

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20251022

Priority Date

20250911

Claims (20)

1. It includes a plurality of components including a first component and a second component, and The first component includes first connection regions on a first surface, and The second component includes second connection regions on the second surface, and At least one of the first connection regions is connected to at least one of the second connection regions, and The first width in the first horizontal direction of the first component substantially corresponds to a first integer multiple of the first basic unit width in the first horizontal direction, and The first width in the first horizontal direction of the second component substantially corresponds to a second integer multiple of the first basic unit width, A semiconductor system characterized in that the second integer multiple is different from the first integer multiple.
2. In paragraph 1, The second width of the first component in the second horizontal direction intersecting the first horizontal direction is substantially the same as the second basic unit width in the second horizontal direction or substantially corresponds to a third integer multiple of the second basic unit width, and A semiconductor system characterized in that the second width of the second component in the second horizontal direction is substantially the same as the second basic unit width in the second horizontal direction or substantially corresponds to a fourth integer multiple of the second basic unit width.
3. In paragraph 1, The vertical thickness of the first component is substantially the same as the basic unit thickness in the vertical direction, or substantially corresponds to a third integer multiple of the basic unit thickness, and A semiconductor system characterized in that the vertical thickness of the second component is substantially the same as the basic unit thickness in the vertical direction or substantially corresponds to a fourth integer multiple of the basic unit thickness.
4. In paragraph 1, The first connection regions are arranged in a first array and have a first size and a first shape, and A semiconductor system characterized in that the second connection regions are arranged in a second array and have the first size and the first shape.
5. In paragraph 1, The spacing between at least two mutually adjacent first connecting regions in the first horizontal direction is, A semiconductor system characterized by having the same spacing as the spacing between at least two mutually adjacent second connection regions in the first horizontal direction.
6. In paragraph 1, The spacing between at least two mutually adjacent first connecting regions in the first horizontal direction is, A semiconductor system characterized by being an integer multiple of the spacing between at least two mutually adjacent second connection regions in the first horizontal direction.
7. In paragraph 1, The spacing between the first connecting regions that are mutually adjacent in the first horizontal direction and The spacing between the second connecting regions that are mutually adjacent in the first horizontal direction is, A semiconductor system characterized by being substantially identical to each of the first integer multiple and the second integer multiple.
8. In paragraph 1, The size and shape of the first connection regions mentioned above are, A semiconductor system characterized by having the same size and shape as the second connection regions mentioned above.
9. In paragraph 1, At least one of the first connection regions includes a plurality of first interconnects arranged in a first array, and A semiconductor system characterized in that at least one of the second connection regions comprises a plurality of second interconnects arranged in a second array.
10. In paragraph 1, Any one of the first component and the second component includes a semiconductor chip, A semiconductor system characterized in that the other of the first component and the second component includes an interposer.
11. In paragraph 1, Either of the first component and the second component comprises a first semiconductor chip configured to perform operations, and A semiconductor system characterized in that the other of the first component and the second component comprises a second semiconductor chip composed of memory.
12. In paragraph 1, The first component further includes third connection regions that overlap with the first connection regions on the second surface of the first component, respectively, and A semiconductor system characterized in that the second component further includes fourth connection regions that overlap with the second connection regions on the second surface of the second component.
13. In paragraph 1, The second width of the first component in the second horizontal direction intersecting the first horizontal direction is substantially the same as the second basic unit width in the second horizontal direction or substantially corresponds to a third integer multiple of the second basic unit width, and The second width of the second component in the second horizontal direction is substantially the same as the second basic unit width in the second horizontal direction or substantially corresponds to a fourth integer multiple of the second basic unit width, and A semiconductor system characterized in that the first connection regions have the same shape and the same size, and the second connection regions also have the same shape and the same size.
14. In paragraph 1, The spacing between the first connecting regions that are mutually adjacent in the first horizontal direction is substantially the same as the spacing between the second connecting regions that are mutually adjacent in the first horizontal direction, and A semiconductor system characterized in that the spacing between mutually adjacent first connection regions in a second horizontal direction intersecting the first horizontal direction is substantially the same as the spacing between mutually adjacent second connection regions in the second horizontal direction.
15. In paragraph 1, A semiconductor system characterized in that the spacing between mutually adjacent first connection regions in the first horizontal direction and the spacing between mutually adjacent second connection regions in the first horizontal direction are substantially equal to the first basic unit width in the first horizontal direction or an integer multiple thereof.
16. In paragraph 1, The above first connection regions are arranged symmetrically, and A semiconductor system characterized in that the above-mentioned second connection regions are arranged symmetrically.
17. In Paragraph 16, One of the first connection areas is connected to another first connection area among the first connection areas through the first component, and A semiconductor system characterized in that the position of the first connection region is symmetric with respect to the position of the other first connection region with respect to a symmetry line passing through the center of the first component in a plan view of the first component.
18. A computer system selects multiple components predefined in at least one library, and The above-mentioned selected plurality of components are arranged by a computer system, and A semiconductor system is manufactured to include a plurality of components included in the above array, and The above plurality of components are, A first component including a first connection area on the first surface and A second component including a second connecting area on the first surface, and In the above arrangement, at least one of the first connection regions is connected to at least one of the second connection regions, and The first width in the first horizontal direction of the first component is substantially the same as a first integer multiple of the first basic unit width in the first horizontal direction, and The first width in the first horizontal direction of the second component is substantially the same as a second integer multiple of the first basic unit width, A method for manufacturing a semiconductor system characterized in that the second integer multiple is different from the first integer multiple.
19. Body; A plurality of first connection regions arranged in a first pattern on a first surface of the body, wherein each of the plurality of first connection regions comprises a plurality of first interconnects arranged in a second pattern; and A plurality of second connection regions arranged in the first pattern on a second surface opposite to the first surface of the body, wherein each of the plurality of second connection regions includes a plurality of second connection regions comprising a plurality of second interconnects arranged in the second pattern. One of the plurality of first interconnects among the plurality of first connection regions above is A plurality of first interconnects of at least one other first connection area or A device configured to electrically connect a plurality of semiconductor components, characterized by being connected to a plurality of second interconnects of at least one second connection region.
20. In Paragraph 19, In one of the plurality of first connection regions above, in At least two of the plurality of first interconnects are wired in different directions, Characterized by being connected to different regions among different first connection regions or second connection regions. A device configured to electrically connect multiple semiconductor components.

Description

Modular Semiconductor System and Method of Manufacturing Thereof The technical concept of the present invention relates to a semiconductor system and a method for manufacturing the same, and more specifically, to a modular semiconductor system and a method for manufacturing the same. A semiconductor system may include multiple interconnected components (e.g., semiconductor devices). For example, the semiconductor system may be a System In Package (SIP) in which multiple components (e.g., semiconductor devices, dies, or semiconductor packages) are packaged together. The information described in the background section of this specification may be technical information already known to or derived by the inventor prior to or during the completion of the embodiments of this application, or acquired during the process of completing the embodiments. Accordingly, this section may include information that does not constitute prior art already known to the public. The embodiments of the present disclosure will be more clearly understood when the following detailed description is referred to in conjunction with the attached drawings. FIG. 1A is a schematic perspective view illustrating a component having basic unit dimensions according to one embodiment of the present disclosure. FIG. 1B is a schematic plan view illustrating the components of FIG. 1A according to one embodiment of the present disclosure. FIG. 2A is a schematic perspective view illustrating the components of a semiconductor system according to one embodiment of the present disclosure. FIG. 2B is a schematic plan view illustrating the components of FIG. 2A according to one embodiment of the present disclosure. FIG. 3A is a schematic plan view according to one embodiment of the present disclosure, illustrating a component in which at least one connecting region is omitted compared to the component shown in FIG. 2A to FIG. 2B. FIG. 3B is a schematic plan view illustrating a first surface of a component configured according to a first set of modular design rules according to one embodiment of the present disclosure. FIG. 3C is a schematic plan view illustrating a second side of a component of FIG. 3B configured according to a second modular design rule set according to one embodiment of the present disclosure. FIG. 4 is a schematic plan view illustrating a connection area of a component of a semiconductor system for connecting to another component, according to one embodiment of the present disclosure. FIG. 5A is a schematic perspective view illustrating a first exemplary interconnect between connection regions of components according to one embodiment of the present disclosure. FIG. 5B is a schematic perspective view illustrating a second exemplary interconnection between connection regions of components according to one embodiment of the present disclosure. FIG. 6A is a schematic plan view illustrating a first horizontal wiring path of a component for transmitting an electrical signal and/or power, according to one embodiment of the present disclosure. FIG. 6B is a schematic plan view illustrating a second horizontal wiring path of a component for transmitting an electrical signal and/or power, according to one embodiment of the present disclosure. FIG. 7 is a schematic cross-sectional view illustrating a semiconductor device including an integrated circuit according to one embodiment of the present disclosure. FIG. 8 is a schematic cross-sectional view illustrating a semiconductor device according to one embodiment of the present disclosure, comprising an integrated circuit and an adapter die for fitting the integrated circuit to a standardized size. FIG. 9A is a schematic plan view illustrating an interposer of a semiconductor system according to one embodiment of the present disclosure. FIG. 9B is a schematic cross-sectional view of an interposer along the line AA' of FIG. 9A according to one embodiment of the present disclosure. FIG. 10A is a schematic side view illustrating a semiconductor system in which two components are vertically stacked, according to one embodiment of the present disclosure. FIG. 10B is a schematic side view illustrating a semiconductor system in which three components are vertically stacked, according to one embodiment of the present disclosure. FIG. 10C is a schematic side view illustrating a semiconductor system having a plurality of components including an interposer stacked thereon, according to one embodiment of the present disclosure. FIG. 10D is a schematic side view illustrating a semiconductor system in which active semiconductor components are stacked, according to one embodiment of the present disclosure. FIG. 11 is a schematic perspective view illustrating a semiconductor system including various components having different functions and sizes, according to one embodiment of the present disclosure. FIG. 12 is a flowchart illustrating a method for manufacturing a semiconductor system according to one embodiment of