KR-20260062892-A - SEMICONDUCTOR PACKAGE AND METHOD FOR FORMING THE SAME

Abstract

A semiconductor package and a method for forming the same are provided. The method comprises the steps of: providing a substrate; mounting a semiconductor die on an upper surface of the substrate; forming a barrier wall on a peripheral region of the upper surface of the semiconductor die; dispensing a first fluid material on the upper surface of the semiconductor die—the barrier wall prevents the first fluid material from flowing across the barrier wall—; and curing the first fluid material to form a back metallized (BSM) layer.

Inventors

• 김, 창오
• 정, 진희
• 최, 영주
• 이, 희수

Assignees

• 스태츠 칩팩 매니지먼트 피티이. 엘티디.

Dates

Publication Date

20260507

Application Date

20251029

Priority Date

20241029

Claims (19)

1. As a method for forming a semiconductor package, Step of providing a substrate; A step of mounting a semiconductor die on the upper surface of the above substrate; A step of forming a barrier wall on a peripheral region of the upper surface of the semiconductor die; A step of dispensing a first fluid material onto the upper surface of the semiconductor die - the barrier wall prevents the first fluid material from flowing across the barrier wall -; and A method comprising the step of curing the first fluid material to form a back metallized (BSM) layer.
2. In paragraph 1, The step of forming the barrier wall on the surrounding region of the upper surface of the semiconductor die is to form the barrier wall on the above-mentioned upper surface of the semiconductor die. A method comprising the step of dispensing a fluid composition onto the upper surface of the semiconductor die using an inkjet printing device, an aerosol printing device, an electrohydroelectric (EHD) printing device, a nozzle printing device, or a spray coating device.
3. In paragraph 1, The step of dispensing the first fluid material onto the upper surface of the semiconductor die is A method comprising the step of dispensing the first fluid material using an inkjet printing device, an aerosol printing device, an electro-hydro (EHD) printing device, a nozzle printing device, or a spray coating device.
4. In paragraph 1, A step of dispensing a second fluid material onto the BSM layer above - the barrier wall prevents the second fluid material from flowing across the barrier wall -; and A method further comprising the step of curing the second fluid material to form a barrier layer on the BSM layer.
5. In paragraph 4, The step of dispensing the second fluid material onto the BSM layer A method comprising the step of dispensing the second fluid material using an inkjet printing device, an aerosol printing device, an electro-hydro (EHD) printing device, a nozzle printing device, or a spray coating device.
6. In paragraph 4, A method in which the BSM layer comprises silver, copper, gold, or aluminum, and the barrier layer comprises nickel, titanium, silicon oxide, aluminum oxide, graphene, boron nitride, or molybdenum sulfide.
7. In paragraph 1, A method further comprising the step of forming an underfill encapsulation agent between the semiconductor die and the substrate.
8. In paragraph 4, A step of providing a thermal interface material (TIM) layer having a lower TIM surface and an upper TIM surface; A step of attaching the lower TIM surface to the barrier layer; and A method further comprising the step of attaching a heat sink to the upper TIM surface.
9. In paragraph 8, The method further includes the step of forming a soldering flux on the lower TIM surface and the upper TIM surface, and A method in which the lower TIM surface is attached to the barrier layer through the soldering flux on the lower TIM surface, and the heat sink is attached to the upper TIM surface through the soldering flux on the upper TIM surface.
10. In paragraph 8, The heat sink comprises a cover and a surface finishing layer attached to the cover, and the heat sink is attached to the TIM layer through the surface finishing layer.
11. In paragraph 8, A method further comprising the step of reflowing the TIM layer to solder the TIM layer and the barrier layer together and to solder the TIM layer and the heatsink together.
12. In paragraph 8, A method in which the above TIM layer comprises indium or an indium-silver alloy.
13. As a semiconductor package, Substrate; A semiconductor die mounted on the upper surface of the above substrate; A barrier wall formed on a peripheral region of the upper surface of the semiconductor die; and A semiconductor package comprising a back metallization (BSM) layer formed on the upper surface of the semiconductor die—the BSM layer being surrounded or partially surrounded by the barrier wall.
14. In Paragraph 13, A semiconductor package further comprising a barrier layer formed on the above BSM layer—the barrier layer being surrounded by or partially surrounded by the barrier wall.
15. In Paragraph 14, A semiconductor package in which the BSM layer comprises silver, copper, gold, or aluminum, and the barrier layer comprises nickel, titanium, silicon oxide, aluminum oxide, graphene, boron nitride, or molybdenum sulfide.
16. In Paragraph 13, A semiconductor package further comprising an underfill encapsulation agent formed between the semiconductor die and the substrate.
17. In Paragraph 14, A thermal interface material (TIM) layer disposed on the barrier layer; and A semiconductor package further comprising a heatsink disposed on the above TIM layer.
18. In Paragraph 17, The above heatsink includes a cover and a surface finishing layer attached to the cover, and the heatsink is a semiconductor package attached to the TIM layer through the surface finishing layer.
19. In Paragraph 17, The above TIM layer is a semiconductor package comprising indium or an indium-silver alloy.

Description

Semiconductor Package and Method for Forming the Same This application generally relates to semiconductor technology, and in particular to a semiconductor package and a method for forming the same. The semiconductor industry continues to face complex integration challenges as consumers demand that their electronic devices become smaller, faster, and higher-performing, with an increasing number of functions packed into a single device. Many electronic components within devices, such as microprocessors and integrated circuits, generate a significant amount of heat during operation. Excessive heat can degrade the performance, reliability, and lifespan of electronic components and may even lead to component failure. Other thermal solutions, including heat sinks, heat spreaders, and thermal interface materials (TIMs), are commonly used to dissipate heat and reduce the operating temperatures of electronic components. However, the efficiency of existing heat dissipation methods may still be limited. Therefore, a semiconductor package with improved heat dissipation capacity is required. The object of the present application is to provide a method for manufacturing a semiconductor package having improved heat dissipation capacity. According to an aspect of the present application, a method for forming a semiconductor package is provided. The method may include the steps of: providing a substrate; mounting a semiconductor die on an upper surface of the substrate; forming a barrier wall on a peripheral region of the upper surface of the semiconductor die; dispensing a first fluid material on the upper surface of the semiconductor die—the barrier wall prevents the first fluid material from flowing across the barrier wall—; and curing the first fluid material to form a back metallized (BSM) layer. According to another aspect of the present application, a semiconductor package is provided. The semiconductor package comprises: a substrate; a semiconductor die mounted on an upper surface of the substrate; a barrier wall formed on a peripheral region of the upper surface of the semiconductor die; and a back metallization (BSM) layer formed on the upper surface of the semiconductor die, wherein the BSM layer is surrounded by the barrier wall or partially surrounded. It should be understood that both the foregoing general description and the following detailed description are merely illustrative and illustrative and do not limit the invention. Additionally, the accompanying drawings, which are included in and constitute part of this specification, serve to illustrate embodiments of the invention and, together with the description, explain the principles of the invention. The drawings referenced herein form part of the specification. The features illustrated in the drawings illustrate only some embodiments of the present application, not all embodiments of the present application, unless expressly otherwise indicated in the detailed description, and readers of the specification should not be interpreted to the contrary. Figure 1 is a microscope image illustrating the back metallization (BSM) layer of a semiconductor package. FIGS. 2a to 2h are plan or cross-sectional views illustrating various steps of a method for forming a semiconductor package according to an embodiment of the present application. FIG. 3 is a cross-sectional view of a semiconductor package according to an embodiment of the present application. Identical reference numbers will be used throughout the drawings to refer to identical or similar parts. The following detailed description of exemplary embodiments of the present application refers to the accompanying drawings, which form part of the description. The drawings illustrate specific exemplary embodiments in which the present application may be practiced. The detailed description including the drawings describes these embodiments in sufficient detail to enable a person skilled in the art to practice the present application. A person skilled in the art may further utilize other embodiments of the present application and may make logical, mechanical, and other modifications without departing from the spirit or scope of the present application. Accordingly, readers of the following detailed description should not interpret the description in a limiting sense, and only the appended claims define the scope of the embodiments of the present application. In this application, the use of the singular includes the plural unless specifically stated otherwise. In this application, the use of "or" means "and/or" unless otherwise stated. Additionally, the use of other forms of terms such as "comprising," "comprising," and "comprising" is not restrictive. Furthermore, terms such as "element" or "component" include all elements and components comprising one unit and all elements and components comprising more than one subunit, unless specifically stated otherwise. Additionally, the section headings used in this specifica