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KR-20260062907-A - DISPLAY DEVICE

KR20260062907AKR 20260062907 AKR20260062907 AKR 20260062907AKR-20260062907-A

Abstract

A display device comprises: a substrate including a display area and a non-display area; pixels provided on the display area and connected to first scan lines, second scan lines, third scan lines, and light emission control lines; a first scan driver provided on the non-display area and supplying a first scan signal to the first scan lines; a second scan driver provided on the non-display area and supplying a second scan signal to a portion of the second scan lines and supplying a third scan signal to the third scan lines; a light emission driver provided on the non-display area and supplying a light emission control signal to the light emission control lines; a first pad and a second pad provided spaced apart from each other on the non-display area; a first power line connected to the first pad and transmitting a first voltage to the first scan driver and the light emission driver; and a second power line connected to the second pad and transmitting a second voltage to the second scan driver.

Inventors

  • 권태훈
  • 이광세
  • 송재진
  • 금낙현
  • 가지현

Assignees

  • 삼성디스플레이 주식회사

Dates

Publication Date
20260507
Application Date
20260403

Claims (20)

  1. Pixels connected to the first scan lines, the second scan lines, the third scan lines, and light emission control lines; A first injection driving unit that provides a first injection signal to the first injection lines; A second injection driving unit that provides a second injection signal to some of the second injection lines and provides a third injection signal to the third injection lines; and It includes a light-emitting driving unit that provides a light-emitting control signal to the light-emitting control lines, and The first scanning drive unit, the second scanning drive unit, and the light-emitting drive unit include a plurality of stages. Each of the above plurality of stages is: An eighth transistor connected between the third power input terminal and the output terminal; and It includes a seventh transistor connected between the second power input terminal and the output terminal, and The source electrode of the seventh transistor and the drain electrode of the eighth transistor are connected to the output terminal, and the output terminal forms a node with a corresponding one of the first scan lines, the second scan lines, the third scan lines, and the light emission control lines, and The drain electrode of the seventh transistor is connected to the second power input terminal, and The source electrode of the eighth transistor is connected to the third power input terminal, and The second power input terminal of the first injection driving unit and the second power input terminal of the light-emitting driving unit are connected to the first power line, and The second power input terminal of the second injection drive unit is connected to a second power line different from the first power line, Display device.
  2. In Article 1, The third power input terminal of the first injection driving unit and the third power input terminal of the light-emitting driving unit are connected to a third power line, and The third power input terminal of the second injection drive unit is connected to a fourth power line different from the third power line, Display device.
  3. In Article 2, The eighth transistor includes a gate electrode connected to the fourth node, and The above seventh transistor includes a gate electrode connected to the third node, and Each of the above plurality of stages is: A 11th transistor connected between the 3rd power input terminal and the 4th node, with its gate electrode connected to the 3rd power input terminal and a 1st node other than the 4th node; A 12th transistor connected between the first node and the third node, with its gate electrode connected to the second power input terminal different from the third node; and A third capacitor further comprising a third capacitor connected between the third power input terminal and the fourth node, Display device.
  4. In Paragraph 3, Each of the above plurality of stages is: A ninth transistor, the first electrode of which is connected to the fourth node and the gate electrode of which is connected to a third input terminal that receives a second clock signal; A 10th transistor connected between the 9th transistor and the 3rd input terminal, with its gate electrode connected to the 5th node; and A 13th transistor further comprising a second node and the fifth node connected between them, with the gate electrode connected to the first power input terminal. Display device.
  5. In Paragraph 4, Each of the above plurality of stages is: A sixth transistor further comprising a second node and a second power input terminal connected between the second node and the second power input terminal, wherein the gate electrode is connected to a second input terminal that receives a first clock signal. Display device.
  6. In Article 5, Each of the above plurality of stages is: A fifth transistor further comprising a second node and a second input terminal connected between the second node and the second input terminal, with the gate electrode connected to the first node. Display device.
  7. In Article 6, Each of the above plurality of stages is: A first capacitor connected to the sixth node; and A third transistor further comprising a third transistor connected between the first capacitor and the third input terminal, with the gate electrode connected to the sixth node. Display device.
  8. In Article 7, Each of the above plurality of stages is: A fourth transistor further comprising a first input terminal connected between the first node and the first input terminal receiving a start pulse or a gate signal of a previous stage, the gate electrode of which is connected to the second input terminal. Display device.
  9. In Article 1, Each of the above pixels is: A fifth pixel transistor connected between a first wiring receiving a first driving voltage and a first pixel node, with a gate electrode connected to one of the light emission control lines; A first pixel transistor connected between the first pixel node and the second pixel node, with its gate electrode connected to the third pixel node; A sixth pixel transistor connected between the second pixel node and the fourth pixel node, with a gate electrode connected to one of the light emission control lines; and A light-emitting element including a second wiring receiving a second driving voltage and a light-emitting element connected between the second wiring receiving the second driving voltage and the fourth pixel node. Display device.
  10. In Article 9, Each of the above pixels is: A storage capacitor connected between the first wiring and the third pixel node; and A second pixel transistor further comprising a data line connected between the first pixel node and a gate electrode connected to one of the first scan lines, Display device.
  11. In Article 10, Each of the above pixels is: A third pixel transistor connected between a third wire receiving a first initialization voltage and the third pixel node, with a gate electrode connected to one of the second scan lines; and A fourth pixel transistor further comprising a second pixel node and a third pixel node connected between them, wherein the gate electrode is connected to one of the third scan lines. Display device.
  12. In Article 11, Each of the above pixels is: A seventh pixel transistor further comprising a fourth wire receiving a second initialization voltage and a fourth pixel node connected thereto, wherein the gate electrode is connected to a fourth scan line. Display device.
  13. In Article 12, The above-mentioned fourth scan line is one of the above-mentioned first scan lines, Display device.
  14. Pixels connected to the first scan lines, the second scan lines, the third scan lines, and light emission control lines; A first injection driving unit that provides a first injection signal to the first injection lines; A second injection driving unit that provides a second injection signal to some of the second injection lines and provides a third injection signal to the third injection lines; and It includes a light-emitting driving unit that provides a light-emitting control signal to the light-emitting control lines, and Each of the above pixels is: A first pixel transistor connected between a first pixel node and a second pixel node, with its gate electrode connected to a third pixel node; A second pixel transistor connected between a data line and the first pixel node, with a gate electrode connected to one of the first scan lines; A third pixel transistor connected between a third wire receiving a first initialization voltage and the third pixel node, with a gate electrode connected to one of the second scan lines; and It includes a fourth pixel transistor connected between the second pixel node and the third pixel node, with a gate electrode connected to one of the third scan lines, and The first injection driving unit and the light-emitting driving unit are connected to a first power line, and The above second injection drive unit is connected to a second power line different from the first power line, Display device.
  15. In Article 14, The above second pixel transistor is a polysilicon semiconductor transistor, and The above third pixel transistor and the above fourth pixel transistor are oxide semiconductor transistors, Display device.
  16. In Article 15, Two adjacent pixel rows of the above pixels are connected to the same one of the second scan lines, and Among the above pixels, the two adjacent pixel rows are connected to the same one of the third scan lines, Display device.
  17. In Article 14, The first injection driving unit and the light-emitting driving unit are connected to a third power line, and The above second injection drive unit is connected to a fourth power line different from the above third power line, Display device.
  18. In Article 17, The first scanning drive unit, the second scanning drive unit, and the light-emitting drive unit include a plurality of stages. Each of the above plurality of stages is: An eighth transistor connected between the third power input terminal and the output terminal; and It includes a seventh transistor connected between the second power input terminal and the output terminal, and The source electrode of the seventh transistor and the drain electrode of the eighth transistor are connected to the output terminal, and the output terminal forms a node with a corresponding one of the first scan lines, the second scan lines, the third scan lines, and the light emission control lines, and The drain electrode of the seventh transistor is connected to the second power input terminal, and The source electrode of the eighth transistor is connected to the third power input terminal, Display device.
  19. In Article 18, The second power input terminal of the first injection driving unit and the second power input terminal of the light-emitting driving unit are connected to the first power line, and The second power input terminal of the second injection drive unit is connected to the second power line. Display device.
  20. In Article 19, The third power input terminal of the first injection driving unit and the third power input terminal of the light-emitting driving unit are connected to the third power line, and The third power input terminal of the second injection drive unit is connected to the fourth power line. Display device.

Description

Display Device The present invention relates to a display device, and more specifically, to a display device comprising a plurality of scanning driving units. The display device includes a data driver, a gate driver, and pixels. The data driver provides data signals to the pixels through data lines. The gate driver generates a gate signal using externally provided gate power voltages and a clock signal, and provides the gate signal to the pixels through gate lines. The gate driver may include a plurality of scanning drivers that output different scanning signals according to the circuit structure of the pixel, and a light-emitting driver that outputs a light-emitting control signal. FIG. 1 is a block diagram showing a display device in embodiments of the present invention. Figure 2 is a circuit diagram showing an example of a pixel included in the display device of Figure 1. Figure 3 is a timing diagram showing an example of signals supplied to the pixel of Figure 2. FIG. 4 is a plan view schematically showing an example of a part of the display device of FIG. 1. FIG. 5 is a plan view schematically showing another example of a part of the display device of FIG. 1. FIG. 6 is a plan view schematically showing another example of a part of the display device of FIG. 1. FIG. 7 is a block diagram showing an example of a gate driving unit included in the display device of FIG. 1. FIG. 8 is a circuit diagram showing an example of the stages of the gate driving unit of FIG. 7. FIG. 9 is a schematic diagram showing an example of a gate driving unit included in the display device of FIG. 1. FIG. 10 is a waveform diagram showing an example of signals output from the gate driver of FIG. 9. FIGS. 11a and FIGS. 11b are drawings showing an example of the connection between the gate driver and the pixel rows of FIG. 9. FIG. 12 is a diagram showing another example of the connection between the gate driver and the pixel rows of FIG. 9. Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions of identical components are omitted. FIG. 1 is a block diagram showing a display device in embodiments of the present invention. Referring to FIG. 1, the display device (1000) may include a pixel unit (100), a gate driving unit (200), a data driving unit (300), and a timing control unit (400). The display device (1000) may further include a power supply unit (500). The display device (1000) can display images at various frame frequencies (refresh rate, driving frequency, or screen refresh rate) depending on driving conditions. The frame frequency is the frequency at which a substantial data voltage is written to the driving transistor of a pixel (PXij) per second. For example, the frame frequency is also called the screen refresh rate or screen refresh frequency, and indicates the frequency at which the display screen is refreshed per second. In one embodiment, the display device (1000) can adjust the output frequency of the gate driver (200) and the corresponding output frequency of the data driver (300) according to driving conditions. For example, the display device (1000) can display images corresponding to various frame frequencies from 1 Hz to 120 Hz. However, as this is exemplary, the display device (1000) can also display images at frame frequencies of 120 Hz or higher (e.g., 240 Hz, 480 Hz). The pixel unit (100) includes scan lines (S1_1 to S1_n, S2_1 to S2_n, S3_1 to S3_n, S4_1 to S4_n), light emission control lines (E1 to En), and data lines (D1 to Dm), and may include pixels (PXij) connected to the scan lines (S1_1 to S1_n, S2_1 to S2_n, S3_1 to S3_n, S4_1 to S4_n), light emission control lines (E1 to En), and data lines (D1 to Dm) (where m and n are integers greater than 1). Each of the pixels (PXij) may include a driving transistor and a plurality of switching transistors. Additionally, the pixels (PXij) may form a plurality of pixel rows in units where the light emission control lines (E1 to En) are connected. For example, pixels (PXij) connected to the first light emission control line (E1) may be represented as the first pixel row. The timing control unit (400) can receive an external input signal from a host system, such as an AP (Application processor), through a predetermined interface. The external input signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, RGB data, and a clock signal. A vertical synchronization signal may include multiple pulses, and based on the time at which each pulse occurs, a previous frame period may end and a current frame period may begin. The interval between adjacent pulses of the vertical synchronization signal may correspond to one frame period. A horizontal synchronization signal may include multiple pulses, and based on the time at which each pul