KR-20260062934-A - Radio frequency interference common mode injection in a C-PHY receiver

KR20260062934AKR 20260062934 AKR20260062934 AKR 20260062934AKR-20260062934-A

Abstract

The input buffer (800) includes a pair of input transistors (802a, 802b) and associated injection circuits (806, 808). The first input transistor (802a) has a source (824a) coupled to a first voltage rail (832) via a first current source (812) and a gate coupled to a first wire (810) of a multi-wire serial bus. Three or more resistors in the first injection circuit (806) couple the wires (832) of the serial bus to a first common node (822a), and the first common node (822a) is coupled to the source (824a) of the first input transistor (802a) by a first capacitor. The second input transistor (802b) has a source (824b) coupled to a first voltage rail (832) via a second current source (814) and a gate coupled to a second wire (820) of the serial bus. Three or more resistors in the second injection circuit (808) connect the wires (832) of the multi-wire serial bus to the second common node (822b), and the second common node (822b) is connected to the source (824b) of the second input transistor (802b) by the second capacitor.

Inventors

데바샤 쉬바라마 판차미
두안 잉
차오 친칭
손 석
샤이크 만수르 바샤
디시트 아브하이

Assignees

퀄컴 인코포레이티드

Dates

Publication Date: 20260507
Application Date: 20240822
Priority Date: 20230906

Claims (20)

As an input buffer, A first input transistor having a source coupled to a first voltage rail through a first current source and a gate coupled to a first wire of a multi-wire serial bus; As a first injection circuit, Three or more resistors configured to connect the wires of the multi-wire serial bus to a common node of the first injection circuit; and The first injection circuit comprising a capacitor configured to connect the common node of the first injection circuit to the source of the first input transistor; A second input transistor having a source coupled to the first voltage rail through a second current source and a gate coupled to the second wire of the multi-wire serial bus; and As a second injection circuit, Three or more resistors configured to connect the wires of the multi-wire serial bus to a common node of the second injection circuit; and An input buffer comprising a second injection circuit, wherein the second injection circuit comprises a capacitor configured to connect the common node of the second injection circuit to the source of the second input transistor.
In claim 1, the input buffer comprises a multi-wire serial bus that includes a 3-wire serial bus operating according to the Mobile Industry Processor Interface (MIPI) Alliance C-PHY protocol.
In paragraph 2, the first injection circuit comprises three resistors, and the first injection circuit is associated with a termination impedance at least five times greater than the characteristic impedance of the 3-wire series bus, an input buffer.
In paragraph 1, An input buffer further comprising a source degeneration circuit configured to combine the source of the first input transistor with the source of the second input transistor.
In paragraph 4, the source degeneration circuit comprises an input buffer including a programmable resistor-capacitor network.
An input buffer according to claim 1, wherein the drain of the first input transistor is coupled to a second voltage rail through a first output resistor, and the drain of the second input transistor is coupled to the second voltage rail through a second output resistor.
In claim 6, the input buffer is provided to a first stage of a differential receiver circuit, and the drains of the first input transistor and the second input transistor are coupled to the inputs of the second stage of the differential receiver circuit.
In paragraph 6, It further includes a source degeneration circuit that combines the source of the first input transistor and the source of the second input transistor, and The above source degeneration circuit is an input buffer configured to control a common mode voltage measured between the drains of the first input transistor and the second input transistor.
In claim 1, the first injection circuit and the second injection circuit are configured to pass signals generated on a 3-wire serial bus by radio frequency interference and to block signals encoded according to the MIPI Alliance C-PHY protocol, an input buffer.
In claim 1, the input buffer is provided to a first differential receiver circuit, and each combination of two wires in a 3-wire serial bus is coupled to one of three differential receiver circuits.
As a method for buffering signals received from a multi-wire serial bus, A step of receiving a first signal through a first wire of a multi-wire serial bus at the gate of a first input transistor, wherein the first input transistor has a source coupled to a first voltage rail through a first current source; A step of receiving a second signal through a second wire of the multi-wire serial bus at the gate of a second input transistor, wherein the second input transistor has a source coupled to the first voltage rail through a second current source; and A step of injecting common mode noise into the sources of the first input transistor and the second input transistor using a first injection circuit and a second injection circuit, The first injection circuit has a capacitor and three or more resistors, each wire of the multi-wire serial bus is connected to a first common node through the three or more resistors of the first injection circuit, and the first common node is connected to the source of the first input transistor through the capacitor of the first injection circuit; and A method for buffering signals received from a multi-wire serial bus, comprising the step of injecting common mode noise, wherein the second injection circuit has a capacitor and three or more resistors, and each wire of the multi-wire serial bus is coupled to a second common node through the three or more resistors of the second injection circuit, and the second common node is coupled to the source of the second input transistor through the capacitor of the second injection circuit.
A method for buffering signals received from a multi-wire serial bus, wherein the multi-wire serial bus comprises a 3-wire serial bus operating according to the Mobile Industry Processor Interface (MIPI) Alliance C-PHY protocol.
A method for buffering signals received from a multi-wire serial bus, wherein, in claim 12, the first injection circuit comprises three resistors, and the first injection circuit is associated with a termination impedance at least five times greater than the characteristic impedance of the 3-wire serial bus.
A method for buffering signals received from a multi-wire serial bus, wherein, in claim 11, the source degeneracy circuit is configured to combine the source of the first input transistor with the source of the second input transistor.
In claim 14, the source degeneration circuit comprises a programmable resistor-capacitor network, a method for buffering signals received from a multi-wire serial bus.
In Paragraph 14, A method for buffering signals received from a multi-wire serial bus, further comprising the step of configuring the source degeneracy circuit to control the common mode voltage measured between the drains of the first input transistor and the second input transistor.
A method for buffering signals received from a multi-wire serial bus, wherein, in claim 11, the drain of the first input transistor is coupled to a second voltage rail through a first output resistor, and the drain of the second input transistor is coupled to the second voltage rail through a second output resistor.
A method for buffering signals received from a multi-wire serial bus, wherein, in claim 17, the first input transistor and the second input transistor are provided to a first stage of a differential receiver circuit, and the drains of the first input transistor and the second input transistor are coupled to the inputs of a second stage of the differential receiver circuit.
A method for buffering signals received from a multi-wire serial bus, wherein, in claim 11, the first injection circuit and the second injection circuit are configured to pass signals generated on a 3-wire serial bus by radio frequency interference and block signals encoded according to the MIPI Alliance C-PHY protocol.
A method for buffering signals received from a multi-wire serial bus, wherein each combination of two wires in a 3-wire serial bus is coupled to one of three differential receiver circuits.

Description

Radio frequency interference common mode injection in a C-PHY receiver Cross-reference regarding related applications This patent application claims priority to pending U.S. Regular Application No. 18/462,107, which was filed on September 6, 2023, assigned to the assignee of this application, and is expressly incorporated herein by reference for all applicable purposes as fully presented below. Technology field The present disclosure generally relates to serial communication over a serial bus in a wireless communication device, and more specifically, to common mode radio frequency interference in a C-PHY interface. Mobile communication devices typically include various components such as circuit boards, IC (integrated circuit) devices, ASIC (application-specific integrated circuit) devices, and/or SoC (System-on-Chip) devices. The types of components may include processing circuits, user interface components, storage, and other peripheral components that communicate via a serial bus. The serial bus may operate according to a standardized or proprietary protocol. In one example, the serial bus may operate according to an Inter-Integrated Circuit ( I2C ) communication protocol. The I2C bus is configured as a multi-drop bus and was developed to connect low-speed peripherals to a processor. The two wires of the I2C bus include the SDA (Serial Data Line), which carries data signals, and the SCL (Serial Clock Line), which carries clock signals. Numerous standards are defined to interconnect specific types of components within mobile communication devices. For example, different types of interfaces may be used for communication between an application processor and display or camera components within a mobile communication device. Some display or camera components employ interfaces that conform to standards or protocols specified by the Mobile Industry Processor Interface (MIPI) Alliance for Camera Serial Interface (CSI) and Display Serial Interface (DSI). MIPI Alliance DSI, DSI-2 (referred to individually or collectively herein as DSI), and CSI and CSI-2 (referred to individually or collectively as CSI) standards define wired interfaces that can be placed within an IC or between certain combinations of IC devices and SoC devices. CSI protocols can be used to combine a camera with an application processor. DSI protocols can be used to combine an application processor with a display subsystem. The low-level physical layer (PHY) interface in each of these applications can be implemented according to MIPI Alliance C-PHY or D-PHY standards and protocols. High-speed and low-power modes of communication are defined for C-PHY and D-PHY interfaces. C-PHY high-speed mode uses low-voltage multiphase signals transmitted in different phases over a 3-wire link. D-PHY high-speed mode uses multiple 2-wire lanes to transmit low-voltage differential signals. The low-power modes of C-PHY and D-PHY interfaces provide lower rates than the high-speed modes and transmit signals at higher voltages. Application processors and associated camera and display subsystems can be subject to electromagnetic interference (EMI) from various sources, including co-located radio frequency (RF) transceivers comprising RF transmitter circuits and antennas. As device technology improves, the combination of demands for higher data rates on serial buses has been met in some cases by increasing the clock rates used to control signaling through serial interfaces. For example, the Version 2.0 specification for MIPI C-PHY interfaces provides transmit clock rates between 4.5 GHz and 6.0 GHz. Increasing transmit clock frequencies can reduce the defined tolerances and margins for data signals and exacerbate the effects of EMI. For these and other reasons, there is a continuing need to improve the ability of high-speed interfaces to eliminate EMI. Specific aspects of the present disclosure relate to systems, devices, methods, and techniques that can improve common mode noise rejection in receivers coupled to a C-PHY 3-wire communication link. In various embodiments of the present disclosure, an input buffer comprises a pair of input transistors and associated injection circuits. A first input transistor has a source coupled to a first voltage rail through a first current source and a gate coupled to a first wire of a multi-wire serial bus. A first injection circuit comprises three or more resistors configured to couple the wires of a multi-wire serial bus to a common node of the first injection circuit. A first injection circuit also comprises a capacitor configured to couple the common node of the first injection circuit to the source of the first input transistor. A second input transistor has a source coupled to a first voltage rail through a second current source and a gate coupled to a second wire of a multi-wire serial bus. A second injection circuit comprises three or more resistors configured to couple the wires of a multi-wire serial bus to a common node