KR-20260063036-A - CIRCUIT BOARD AND PACKAGE SUBSTRATE HAVING THE SAME

KR20260063036AKR 20260063036 AKR20260063036 AKR 20260063036AKR-20260063036-A

Abstract

An embodiment of the present invention discloses a circuit board comprising: a first insulating layer; a second insulating layer disposed on the first insulating layer; a capacitor structure disposed between the first insulating layer and the second insulating layer; a first via electrode penetrating the first insulating layer; and a plurality of second via electrodes penetrating the second insulating layer, wherein the plurality of second via electrodes are connected to the capacitor structure and at least one is a dummy electrode.

Inventors

송진호
라세웅
이기한

Assignees

엘지이노텍 주식회사

Dates

Publication Date: 20260507
Application Date: 20241030

Claims (17)

First insulating layer; A second insulating layer disposed on the first insulating layer; A capacitor structure disposed between the first insulating layer and the second insulating layer; A first via electrode penetrating the first insulating layer; and It includes a plurality of second via electrodes penetrating the second insulating layer; and The plurality of second via electrodes are circuit boards connected to the capacitor structure.
In paragraph 1, The above capacitor structure is, A circuit board comprising a first via land disposed on the first insulating layer, a plurality of dielectric layers disposed on the first via land, and a plurality of second via lands disposed on the plurality of dielectric layers.
In paragraph 2, A circuit board in which at least one of the plurality of second via electrodes is a dummy electrode.
In paragraph 3, The plurality of dielectric layers are arranged on a circuit board spaced apart from each other in a horizontal direction on the first via land.
In paragraph 4, The plurality of second via lands are circuit boards spaced apart from each other in the horizontal direction on corresponding dielectric layers among the plurality of dielectric layers.
In paragraph 3, The above plurality of second via electrodes are, A plurality of first sub-electrodes disposed between the plurality of second vialands and the upper surface of the second insulating layer; and A circuit board comprising: a second sub-electrode disposed between the first via land and the upper surface of the second insulating layer.
In paragraph 6, A circuit board in which one of the plurality of first sub-electrodes is a dummy electrode.
In paragraph 6, At least two of the plurality of first sub-electrodes are connected to each other, forming a circuit board.
In paragraph 2, The above plurality of first sub-electrodes are circuit boards with equal lengths in the vertical direction.
In paragraph 2, The above plurality of second via lands are circuit boards having different areas.
In paragraph 2, A circuit board in which the area of the first via land is larger than the area of the plurality of second via lands.
In paragraph 6, It further includes a first wiring portion disposed on the first insulating layer; and The second via electrode is a circuit board disposed between the upper surface of the first insulating layer and the upper surface of the second insulating layer.
In Paragraph 12, The second via electrode above is, A circuit board comprising: a third sub-electrode disposed between the upper surface of the first wiring section and the second insulating layer.
In Paragraph 13, A circuit board in which the length of the third sub-electrode is greater than the lengths of the first sub-electrode and the second sub-electrode.
In Paragraph 13, A circuit board in which the length of the second sub-electrode is greater than the length of the first sub-electrode.
In paragraph 2, A circuit board in which the area of the first via land is larger than the area of the plurality of dielectric layers.
In paragraph 2, A circuit board having different areas of the plurality of dielectric layers.

Description

Circuit board and semiconductor package having the same An embodiment according to the present invention relates to a circuit board and a semiconductor package. As the performance of electrical and electronic products advances, technologies are being proposed and researched to attach a larger number of packages to substrates of limited size. However, since conventional packages are based on mounting a single semiconductor chip, there are limitations in achieving the desired performance. A typical circuit board or package board consists of a processor package housing a processor chip and a memory package housing a memory chip, connected as a single unit. By manufacturing the processor and memory chips into a single integrated package, such package boards offer the advantages of reducing the chip mounting area and enabling high-speed signals through short paths. Due to these benefits, such package boards are widely applied in mobile devices and the like. Meanwhile, recently, the size of packages has been increasing due to the high specifications of electronic devices such as mobile devices and the adoption of High Bandwidth Memory (HBM). In addition, as the functions required of application processors increase, there is a demand for circuit boards capable of mounting these processor chips, which are configured as separate processor chips for each function. At this time, even when the application processor is separated into two processor chips for each function, the number of terminals (Input/Output) provided on each processor chip is increasing. In addition, due to recent factors such as 5G, the Internet of Things (IoT), improved image quality, and increased communication speeds, the number of terminals on processor chips is gradually increasing as the number of power and signals grows. Consequently, the area, thickness, and circuit pattern density of the circuit board are also increasing. However, increasing the area and thickness of the circuit board can lead to difficulties in miniaturizing the product, as well as issues such as reliability problems like board warping and increased product costs. Therefore, rather than increasing the area and thickness of the circuit board, increasing the circuit pattern density is more advantageous in terms of product cost, reliability (such as warping), and miniaturization. Consequently, miniaturization of circuit patterns and through-electrodes is required. Furthermore, the current practice involves mounting structures with specific component characteristics (e.g., capacitors) onto circuit boards to gain advantages in signal characteristics and the like. Consequently, there is an increasing demand for more accurate component characteristics. FIG. 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, and FIG. 2 is an enlarged view of the K1 portion in FIG. 1, and FIG. 3 is a schematic diagram with the second insulating layer removed from FIG. 2, and FIG. 4 is a plan view of a sub-electrode first via land and a second via land in a circuit board according to an embodiment, and FIGS. 5 and 6 are drawings illustrating various examples of electrical connections between a plurality of first sub-electrodes in FIG. 2, and FIG. 7 is an enlarged view of the K2 portion in FIG. 1, and FIGS. 8 to 12 are drawings illustrating a method for manufacturing a circuit board according to a first embodiment, and FIG. 13 is a cross-sectional view of a circuit board according to a second embodiment of the present invention, and FIG. 14 is an enlarged view of the K3 portion in FIG. 13, and FIG. 15 is a cross-sectional view showing a semiconductor package according to a first embodiment, and FIG. 16 is a cross-sectional view showing a semiconductor package according to a second embodiment, and FIG. 17 is a cross-sectional view showing a semiconductor package according to a third embodiment, and FIG. 18 is a cross-sectional view showing a semiconductor package according to a fourth embodiment. The present invention is susceptible to various modifications and may have various embodiments, and specific embodiments are illustrated and described in the drawings. However, this does not specify the present invention. It should be understood that the embodiments are not intended to be limited and include all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted. In addition, terms used in the embodiments of the present invention (including technical and scient