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KR-20260063037-A - CIRCUIT BOARD AND PACKAGE SUBSTRATE HAVING THE SAME

KR20260063037AKR 20260063037 AKR20260063037 AKR 20260063037AKR-20260063037-A

Abstract

An embodiment of the present invention discloses a circuit board comprising: a first insulating layer; and a second insulating layer disposed on the first insulating layer, wherein the second insulating layer comprises a projection disposed in a dummy trench penetrating to at least a portion of the first insulating layer, and the coefficient of thermal expansion of the first insulating layer is smaller than the coefficient of thermal expansion of the second insulating layer.

Inventors

  • 송진호
  • 라세웅
  • 이기한

Assignees

  • 엘지이노텍 주식회사

Dates

Publication Date
20260507
Application Date
20241030

Claims (17)

  1. First insulating layer; and A second insulating layer disposed on the first insulating layer; comprising The second insulating layer includes a projection disposed in a dummy trench penetrating to at least a portion of the first insulating layer, and A circuit board in which the second via electrode in the second insulating layer and the first via electrode in the first insulating layer have different angles of inclination with respect to the upper surface of the first insulating layer.
  2. In paragraph 1, The first via electrode is a circuit board penetrating the first insulating layer.
  3. In paragraph 1, The above first via electrode is a circuit board in which at least a portion overlaps horizontally with the dummy trench.
  4. In paragraph 1, A circuit board in which the length in the vertical direction of the first via electrode is greater than the length in the vertical direction of the dummy trench.
  5. In paragraph 1, A circuit board in which the dielectric constant of the first insulating layer is greater than the dielectric constant of the second insulating layer.
  6. In paragraph 1, A circuit board in which the first insulating layer and the second insulating layer are made of different materials.
  7. In paragraph 1, The above first insulating layer comprises a first filler, a first resin, and fibers, and The above second insulating layer is a circuit board comprising a second filler and a second resin.
  8. In Paragraph 7, The above dummy trench is a circuit board in contact with the above fiber.
  9. In Paragraph 7, The above dummy trench is a circuit board located on top of the fiber.
  10. In paragraph 1, A circuit board in which the thickness of the first insulating layer is greater than the thickness of the second insulating layer.
  11. In paragraph 1, A capacitor structure disposed on the first insulating layer; further comprising The above dummy trench is a circuit board that overlaps vertically with the above capacitor structure.
  12. In paragraph 1, It further includes an inductor structure disposed on the first insulating layer; The above dummy trench is a circuit board that overlaps vertically with the above inductor structure.
  13. In paragraph 1, A circuit board further comprising a dummy member surrounding the above-mentioned dummy trench.
  14. In Paragraph 13, The above dummy member is a circuit board disposed on the upper surface of the first insulating layer.
  15. In Paragraph 13, It further includes a first wiring portion disposed on the upper surface of the first insulating layer; and A circuit board in which the thickness of the first wiring section is the same as the thickness of the dummy member.
  16. In paragraph 1, A circuit board in which the first via electrode and the second via electrode have opposite directions of increasing width.
  17. In paragraph 1, A circuit board in which the coefficient of thermal expansion of the first insulating layer is smaller than the coefficient of thermal expansion of the second insulating layer.

Description

Circuit board and semiconductor package having the same An embodiment according to the present invention relates to a circuit board and a semiconductor package. As the performance of electrical and electronic products advances, technologies are being proposed and researched to attach a larger number of packages to substrates of limited size. However, since conventional packages are based on mounting a single semiconductor chip, there are limitations in achieving the desired performance. A typical circuit board or package board consists of a processor package housing a processor chip and a memory package housing a memory chip, connected as a single unit. By manufacturing the processor and memory chips into a single integrated package, such package boards offer the advantages of reducing the chip mounting area and enabling high-speed signals through short paths. Due to these benefits, such package boards are widely applied in mobile devices and the like. Meanwhile, recently, the size of packages has been increasing due to the high specifications of electronic devices such as mobile devices and the adoption of High Bandwidth Memory (HBM). In addition, as the functions required of application processors increase, there is a demand for circuit boards capable of mounting these processor chips, which are configured as separate processor chips for each function. At this time, even when the application processor is separated into two processor chips for each function, the number of terminals (Input/Output) provided on each processor chip is increasing. In addition, due to recent factors such as 5G, the Internet of Things (IoT), improved image quality, and increased communication speeds, the number of terminals on processor chips is gradually increasing as the number of power and signals grows. Consequently, the area, thickness, and circuit pattern density of the circuit board are also increasing. However, increasing the area and thickness of the circuit board can lead to difficulties in miniaturizing the product, as well as issues such as reliability problems like board warping and increased product costs. Therefore, rather than increasing the area and thickness of the circuit board, increasing the circuit pattern density is more advantageous in terms of product cost, reliability (such as warping), and miniaturization. Consequently, miniaturization of circuit patterns and through-electrodes is required. Recently, as the demand for the development of circuit boards to minimize the thickness of electronic products increases, the development of composite boards with stacked heterogeneous materials is emerging to reduce thickness while minimizing signal loss within the board. FIG. 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, and FIG. 2 is an enlarged view of the K1 portion in FIG. 1, and FIG. 3 is a modified example of FIG. 2, and FIG. 4 is a plan view of a first insulating layer, a first wiring portion, and a dummy trench in a circuit board according to an embodiment, and FIG. 5 is a cross-sectional view of a circuit board with a capacitor structure embedded therein according to an embodiment, and FIG. 6 is a plan view of some components of FIG. 5, and FIG. 7 is a modified example of FIG. 5, and FIG. 8 is a cross-sectional view of an inductor structure embedded in a circuit board according to an embodiment, and FIG. 9 is a plan view of some components of FIG. 8, and FIG. 10 is a drawing illustrating a method for manufacturing a circuit board according to a first embodiment of the present invention, and FIG. 11 is a cross-sectional view of a circuit board according to a second embodiment of the present invention, and FIG. 12 is a drawing illustrating the structure of a first insulating layer, a dummy member, and a second insulating layer in a circuit board according to a second embodiment, and FIG. 13 is a plan view of a dummy member, a dummy trench, and a first insulating layer in a circuit board according to a second embodiment of the present invention, and FIG. 14 is a plan view of a strip of a circuit board according to an embodiment of the present invention, and FIG. 15 is an example of an enlarged view of a portion of FIG. 14, and FIG. 16 is a diagram illustrating a manufacturing sequence for laminating a first insulating layer, a dummy member, and a second insulating layer on a circuit board according to a second embodiment, and FIG. 17 is a cross-sectional view showing a semiconductor package according to a first embodiment, and FIG. 18 is a cross-sectional view showing a semiconductor package according to a second embodiment, and FIG. 19 is a cross-sectional view showing a semiconductor package according to a third embodiment, and FIG. 20 is a cross-sectional view showing a semiconductor package according to a fourth embodiment. The present invention is susceptible to various modifications and may have various embodiments, and specific embodiments are