KR-20260063040-A - SEMICONDUCTOR DEVICES

KR20260063040AKR 20260063040 AKR20260063040 AKR 20260063040AKR-20260063040-A

Abstract

A semiconductor device according to embodiments of the present invention comprises: a first structure including a substrate; and The device includes a second structure that is vertically superimposed with the first structure and includes peripheral circuits, wherein the first structure comprises: a device isolation structure disposed within the substrate; channel structures extending in a first horizontal direction on the substrate and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; an insulation pattern between the channel structures; bit lines extending in a vertical direction on the substrate and contacting a first end of each of the channel structures; a gate electrode extending in the second horizontal direction and surrounding the channel structures; information storage structures contacting the second ends of the channel structures opposite to the first ends of the channel structures and spaced apart from each other in the second horizontal direction; and a plate electrode connected to the information storage structures and extending in the second horizontal direction and the vertical direction, wherein the device isolation structure comprises: a first device isolation pattern vertically superimposed with the bit lines; and a second device isolation pattern vertically superimposed with the plate electrode. and includes third element isolation patterns that overlap perpendicularly with the insulation pattern and are spaced apart from each other in the second horizontal direction between the first element isolation pattern and the second element isolation pattern, and at least one of the first element isolation pattern, the second element isolation pattern, and the third element isolation patterns can penetrate the substrate.

Inventors

김유진
한진우

Assignees

삼성전자주식회사

Dates

Publication Date: 20260507
Application Date: 20241030

Claims (10)

A first structure including a substrate; and It includes a second structure that is vertically superimposed with the first structure and includes a peripheral circuit, and The above-mentioned first structure is, A device isolation structure disposed within the above substrate; Channel structures extending in a first horizontal direction on the substrate and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; Insulation pattern between the above channel structures; Bit lines extending vertically on the substrate and contacting each first end of the channel structures; A gate electrode extending in the second horizontal direction and surrounding the channel structures; Information storage structures that are in contact with the second ends of the channel structures opposite to the first ends of the channel structures and are spaced apart from each other in the second horizontal direction; and It includes a plate electrode connected to the information storage structures and extending in the second horizontal direction and the vertical direction, The above-mentioned device isolation structure is, A first element isolation pattern that overlaps vertically with the above bit lines; A second element isolation pattern vertically superimposed with the above plate electrode; and It includes third element isolation patterns that overlap vertically with the insulation pattern and are spaced apart from each other in the second horizontal direction between the first element isolation pattern and the second element isolation pattern. A semiconductor device having at least one of the first element isolation pattern, the second element isolation pattern, and the third element isolation pattern penetrating the substrate.
In Article 1, A semiconductor device in which at least one of the lower surface of the first device isolation pattern, the lower surface of the second device isolation pattern, and the lower surface of the third device isolation patterns is coplanar with the lower surface of the substrate.
In Article 1, The first element isolation pattern extends in the second horizontal direction and has an upper surface in contact with the lower surface of the bit lines, A semiconductor device having a second element isolation pattern that extends in the second horizontal direction and has an upper surface in contact with the lower surface of the plate electrode.
In Article 1, The first element separation pattern above has a first width in the first horizontal direction, and Each of the above third element separation patterns has a second width smaller than the first width in the second horizontal direction, a semiconductor device.
In Article 1, A semiconductor device in which the upper surface of the first element isolation pattern and the upper surface of the second element isolation pattern are positioned at a higher level than the upper surface of the substrate.
In Article 1, A semiconductor device in which the lower surface of the first element isolation pattern, the lower surface of the second element isolation pattern, and the lower surface of the third element isolation patterns are exposed from the lower surface of the substrate.
A substrate having a first region and a second region; A device isolation structure disposed within the above substrate; Channel structures extending in a first horizontal direction on the first region of the substrate and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction and a vertical direction intersecting the first horizontal direction and the second horizontal direction; Bit lines extending in a vertical direction on the first region of the substrate, spaced apart from each other in the second horizontal direction, and contacting the first end of each of the channel structures; Gate electrodes comprising gate pads that surround the channel structures spaced apart from each other in the second horizontal direction, extend in the second horizontal direction, and are arranged in a stepped shape on the second region; Information storage structures in contact with the second ends of the channel structures facing the first ends of the channel structures; and It includes a plate electrode connected to the information storage structures and extending in the second horizontal direction and the vertical direction, The above-mentioned device isolation structure is, A first element isolation pattern vertically overlapping the bit lines; and It includes a second element isolation pattern that overlaps vertically with the above plate electrode, and A semiconductor device in which at least one of the lower surface of the first element isolation pattern and the lower surface of the second element isolation pattern is coplanar with the lower surface of the substrate.
In Article 7, A semiconductor device wherein each of the first element isolation pattern and the second element isolation pattern extends in the second horizontal direction and is disposed on the first region and the second region.
In Article 7, It further includes third element isolation patterns disposed between the first element isolation pattern and the second element isolation pattern and spaced apart from each other in the second horizontal direction, The above third element isolation patterns do not overlap with the channel structures in the vertical direction, semiconductor device.
A first structure comprising a substrate including a first region; and It includes a second structure that overlaps vertically with the first structure and includes a peripheral circuit area, and The above-mentioned first structure is, A device isolation structure disposed within the above substrate; Channel structures extending in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; each of the channel structures includes a channel region and first and second source/drain regions separated by the channel region; Insulation pattern between the above channel structures; Bit lines extending in a vertical direction and contacting the first end of each of the channel structures; A gate dielectric layer extending in the second horizontal direction and surrounding the channel region of the channel structures; A gate electrode extending in the second horizontal direction and surrounding the gate dielectric layer; Information storage structures in contact with the second ends of the channel structures facing the first ends of the channel structures; and It includes a plate electrode connected to the information storage structures and extending in the second horizontal direction and the vertical direction, The above-mentioned device isolation structure is, A first element isolation pattern having an upper surface in contact with the lower surface of the bit lines and extending in the second horizontal direction; A second element isolation pattern having an upper surface in contact with the lower surface of the plate electrode and extending in the second horizontal direction; and It includes third element isolation patterns that overlap perpendicularly with the insulation pattern, extend in the first horizontal direction between the first element isolation pattern and the second element isolation pattern, and are spaced apart from each other in the second horizontal direction. A semiconductor device having at least one of the first element isolation pattern, the second element isolation pattern, and the third element isolation pattern penetrating the substrate.

Description

Semiconductor Devices The present invention relates to a semiconductor device. Specifically, it relates to a semiconductor device comprising three-dimensional channel structures. As the demand for high performance, high speed, and/or multifunctionality of semiconductor devices increases, the integration density of semiconductor devices is increasing. In the case of conventional two-dimensional or planar semiconductor devices, the integration density is mainly determined by the area occupied by the unit memory cell array region, and thus is influenced by the level of fine pattern formation technology. Accordingly, three-dimensional semiconductor devices including memory cells arranged in three dimensions are being proposed. FIG. 1 is a schematic perspective view of a semiconductor device according to embodiments of the present invention. FIG. 2 is a circuit diagram of a memory cell in a memory cell array region according to embodiments of the present invention. FIG. 3 is a schematic plan view of a semiconductor device according to one embodiment. FIG. 4 is a perspective view of a semiconductor device according to one embodiment. Figure 5 is a vertical cross-sectional view along line I-I' of the semiconductor device shown in Figure 3. Figure 6 is a vertical cross-sectional view along line II-II' of the semiconductor device shown in Figure 3. Figure 7 is a vertical cross-sectional view along line III-III' of the semiconductor device shown in Figure 3. FIG. 8a is a partial enlarged view according to one embodiment of the semiconductor device shown in FIG. 5. FIG. 8b is a partial enlarged view according to one embodiment of the semiconductor device shown in FIG. 6. FIG. 9a is a partial enlarged view according to another embodiment of the semiconductor device shown in FIG. 5. FIG. 9b is a partial enlarged view according to another embodiment of the semiconductor device shown in FIG. 6. FIG. 10 is a partial enlarged view according to another embodiment of the semiconductor device shown in FIG. 6. FIGS. 11, FIGS. 12, and FIGS. 13 are enlarged views of some embodiments of the semiconductor device shown in FIG. 5. Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions of identical components are omitted. FIG. 1 is a schematic perspective view of a semiconductor device according to embodiments of the present invention. Referring to FIG. 1, the semiconductor device (100) may include a first structure (ST1) and a second structure (ST2) that overlaps vertically with the first structure (ST1). The second structure (ST2) may be placed on the first structure (ST1). The first structure (ST1) may be a first chip structure including memory cells (MC), and the second structure (ST2) may be a second structure (ST2) including peripheral circuits capable of operating the memory cells (MC). The first structure (ST1) and the second structure (ST2) may be formed by joining through a bonding process such as a wafer bonding process. Accordingly, the first structure (ST1) may be joined to the second structure (ST2) in contact with it. A semiconductor device (100) may include a plurality of banks (BA) and a peripheral circuit region (PERI). The peripheral circuit region (PERI) may include a first peripheral circuit region (PERI1) within a first structure (ST1) and a second peripheral circuit region (PERI2) within a second structure (ST2). The peripheral circuit region (PERI) may be a peripheral circuit region where peripheral circuits for input/output of data or commands, or input of power/ground, are arranged. Each of the plurality of banks (BA) may include a first bank area (BA1) within the first structure (ST1) and a second bank area (BA2) within the second structure (ST2). A first bank region (BA1) within a first structure (ST1) may include memory cell array regions. The memory cell array regions may include memory cells (MC). The memory cell array regions may be arranged along a first direction (X direction) and a second direction (Y direction). The first direction (X direction) and the second direction (Y direction) may be perpendicular to each other. The first direction (X direction) and the second direction (Y direction) may be referred to as horizontal directions, and the third direction (Z direction) may be referred to as vertical directions. The second bank region (BA2) within the second structure (ST2) may include core circuit regions. The core circuit regions may be arranged along a first direction (X direction) and a second direction (Y direction). The core circuit regions may include sense amplifiers and sub-wordline drivers. The first peripheral circuit region (PERI1) and the second peripheral circuit region (PERI2) may include a control circuit capable of controlling the sense amplifier and the sub-wordline driver. FIG. 2 is a circuit di