KR-20260063152-A - SEMICONDUCTOR DEVICES

Abstract

A semiconductor device comprises a gate structure, channels each extending in a first direction through the gate structure and spaced apart from each other along a second direction orthogonal to the first direction, a source/drain layer formed on one side of the gate structure in the first direction and in contact with the channels, an insulating material, a first spacer formed on a side wall of the gate structure in the first direction, and a semiconductor material, and a second spacer formed on the side wall of the first spacer in the first direction and in contact with the source/drain layer, wherein the width of the first spacer in the first direction may increase from both edge portions in the second direction toward the center.

Inventors

• 허준
• 김주연
• 오세웅
• 강민형
• 홍수헌
• 김형수
• 신기웅
• 윤현기
• 최준혁

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20241030

Claims (10)

1. Gate structure; Channels each extending in a first direction through the gate structure and spaced apart from each other along a second direction orthogonal to the first direction; A source/drain layer formed on one side of the gate structure in the first direction and in contact with the channels; A first spacer comprising an insulating material and formed on the sidewall of the gate structure in the first direction; and It includes a semiconductor material and a second spacer formed on the sidewall of the first spacer in the first direction and in contact with the source/drain layer, and A semiconductor device in which the width of the first spacer in the first direction increases from the two edge portions in the second direction toward the center.
2. In claim 1, the source/drain layer comprises a first epitaxial layer including a first semiconductor material having a first impurity concentration; and A semiconductor device having a second epitaxial layer that covers the sidewall of the first epitaxial layer and includes a second semiconductor material having a second impurity concentration lower than the first impurity concentration.
3. In paragraph 2, the second semiconductor material included in the second epitaxial layer is a semiconductor device having a continuous crystal structure.
4. In claim 1, the first spacer comprises a first sidewall and a second sidewall facing each other in the first direction, and the second spacer is formed on the second sidewall of the first spacer. A semiconductor device in which each of the first sidewall and the second sidewall of the first spacer is convex toward the gate structure.
5. A semiconductor device according to claim 4, wherein the first sidewall of the first spacer has a first curvature, and the second sidewall of the first spacer has a second curvature smaller than the first curvature.
6. In paragraph 4, the second spacer comprises a first side wall and a second side wall facing each other in the first direction, and The first side wall of the second spacer contacts the second side wall of the first spacer, and The second sidewall of the second spacer is a semiconductor device in contact with the source/drain layer.
7. In claim 6, each of the first sidewall and the second sidewall of the second spacer is a semiconductor device convex toward the gate structure.
8. Channels extending in a first direction and spaced apart from each other along a second direction orthogonal to the first direction; A gate structure that at least partially surrounds the upper and lower surfaces and side walls of each of the above channels; A source/drain layer formed on one side of the gate structure in the first direction and in contact with the channels; and It includes a first spacer and a second spacer sequentially stacked on the side wall in the first direction of the gate structure, The above second spacer is a semiconductor device that overlaps at least partially with one of the channels in the first direction.
9. In claim 8, the first spacer comprises silicon nitride, and The above second spacer is a semiconductor device comprising a semiconductor material.
10. An active pattern formed on a substrate and extending in a first direction parallel to the upper surface of the substrate; A gate structure formed on the active pattern and extending in a second direction parallel to the upper surface of the substrate and intersecting the first direction; Channels spaced apart from each other along a vertical direction perpendicular to the upper surface of the substrate, each penetrating the gate structure; A first epitaxial layer formed on the active pattern portion adjacent to the gate structure in the first direction and comprising a first semiconductor material having a first impurity concentration; and A source/drain layer comprising a second epitaxial layer that contacts the sidewall of the first epitaxial layer, has a second impurity concentration lower than the first impurity concentration, and includes a second semiconductor material having a continuous crystal structure; A first spacer formed on the sidewall in the first direction of the gate structure and comprising silicon nitride; and A semiconductor device having a second spacer formed on the side wall in the first direction of the first spacer and comprising a semiconductor material.

Description

Semiconductor Devices The present invention relates to a semiconductor device. A semiconductor device may include a gate structure and source/drain layers formed on both sides thereof. Since leakage current may occur between the gate structure and the source/drain layers, internal spacers may be formed on the side walls of the gate structure to prevent this. FIGS. 1 to 6 are plan and cross-sectional views for illustrating a semiconductor device according to exemplary embodiments. FIGS. 7 to 26 are plan and cross-sectional views illustrating a method for manufacturing a semiconductor device according to exemplary embodiments. Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. In the following detailed description of the invention (excluding claims), two directions that intersect each other among the horizontal directions parallel to the upper surface of the substrate are defined as the first and second directions (D1, D2), respectively, and a vertical direction perpendicular to the upper surface of the substrate is defined as the third direction (D3). In exemplary embodiments, the first and second directions (D1, D2) may be orthogonal to each other. Meanwhile, each of the first to third directions (D1, D2, D3) may mean not only the direction shown in the drawing but also the opposite direction. [Example] FIGS. 1 to 6 are plan and cross-sectional views for illustrating a semiconductor device according to exemplary embodiments. Specifically, FIG. 1 is a plan view, and FIGS. 2 to 6 are cross-sectional views. FIG. 2 is a cross-sectional view cut along line A-A' of FIG. 1, FIG. 3 is a cross-sectional view cut along line B-B' of FIG. 1, FIG. 4 is a cross-sectional view cut along line C-C' of FIG. 1, and FIGS. 5 and 6 are enlarged cross-sectional views of region X of FIG. 1. Referring to FIGS. 1 to 6, the semiconductor device may include an active pattern (105) formed on a substrate (100), a device isolation pattern (130), semiconductor patterns (124), first and second spacers (200, 205), a gate spacer (180), a source/drain layer (220), a gate structure (300), first and second contact plugs (370, 390), first and second interlayer insulating films (230, 380), and vias (400). The substrate (100) may include, for example, silicon, germanium, silicon-germanium, or group III-V compounds such as GaP, GaAs, GaSb, etc. According to some embodiments, the substrate (100) may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. The active pattern (105) may protrude above the substrate (100), and its sidewall may be covered by the device isolation pattern (130). In exemplary embodiments, the active pattern (105) may be extended in a first direction (D1) and may be formed in multiple numbers spaced apart from each other along a second direction (D2). In exemplary embodiments, the device isolation pattern (130) may extend in a first direction (D1) between two active patterns (105) adjacent to each other in a second direction (D2), and may be formed in multiple numbers spaced apart from each other along the second direction (D2). The active pattern (105) may include a material substantially identical to the substrate (100), and the device isolation pattern (130) may include an oxide, for example, silicon oxide. The semiconductor patterns (124) may be formed on a plurality of layers spaced apart from each other along a third direction (D3) from the upper surface of the active pattern (105), and each may be extended by a certain length in a first direction (D1). Although the semiconductor patterns (124) are shown formed on three layers in the drawing, the concept of the present invention is not limited thereto and may be formed on more or fewer layers. Additionally, in the drawing, two semiconductor patterns (124) spaced apart from each other in the first direction (D1) are shown formed on each layer of the active pattern (105) extending in the first direction (D1), but the concept of the present invention is not limited thereto, and any plurality of semiconductor patterns (124) spaced apart from each other along the first direction (D1) may be formed. In exemplary embodiments, the semiconductor pattern (124) may be a nano-sheet containing silicon or a nano-wire. In exemplary embodiments, the semiconductor pattern (124) may serve as a channel of a transistor containing it and may be referred to as a channel accordingly. The gate structure (300) may extend in a second direction (D2) on the active pattern (105) and the device isolation pattern (130), and may include a gate insulation pattern (270), a gate electrode (280), and a capping pattern (290). In exemplary embodiments, the gate structure (300) may surround the central portion of each semiconductor pattern (124) in the first direction (D1) and may cover the upper and lower surfaces of the central portion of each semiconductor pattern (124) and both side walls in