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KR-20260063156-A - WIRING STRUCTURES AND METHODS OF MANUFACTURING THE SAME

KR20260063156AKR 20260063156 AKR20260063156 AKR 20260063156AKR-20260063156-A

Abstract

A wiring structure comprises: a via formed on a substrate; a first wiring that contacts the upper surface of the via and extends by a first length in a first direction parallel to the upper surface of the substrate; and a second wiring that is spaced apart from the first wiring in the first direction and extends by a second length in the first direction that is smaller than the first length. The structure includes an interlayer insulating film that accommodates the first and second wirings, wherein the interlayer insulating film interposed between the first and second wirings has a first sidewall that contacts the first wiring in the first direction and a second sidewall that contacts the second wiring in the first direction, wherein the sign of the slope of the first lower portion of the first sidewall and the sign of the slope of the first upper portion of the first sidewall are opposite to each other, and the sign of the slope of the second lower portion, the second central portion, and the second upper portion of the second sidewall are all the same as the slope of the first lower portion of the first sidewall, and the absolute value of the average slope of the second upper portion of the second sidewall is smaller than the absolute value of the average slope of the second central portion of the second sidewall.

Inventors

  • 오지수
  • 김기일
  • 전경엽

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260507
Application Date
20241030

Claims (10)

  1. via formed on a substrate; A first wiring that contacts the upper surface of the via and extends by a first length in a first direction parallel to the upper surface of the substrate; A second wiring spaced apart from the first wiring in the first direction and extended in the first direction by a second length smaller than the first length; and It includes an interlayer insulating film that accommodates the first and second wirings, and The interlayer insulating film interposed between the first and second wirings has a first sidewall in contact with the first wiring in the first direction, and a second sidewall in contact with the second wiring in the first direction. The sign of the slope of the first lower part of the first side wall and the sign of the slope of the first upper part of the first side wall are opposite to each other, and A wiring structure in which the sign of the slope of each of the second lower, second central, and second upper portions of the second side wall is the same as the slope of the first lower portion of the first side wall, and the absolute value of the average slope of the second upper portion of the second side wall is smaller than the absolute value of the average slope of the second central portion of the second side wall.
  2. In claim 1, the first lower and first upper portions of the first side wall are continuous, and the second lower portion, second central portion, and second upper portion of the second side wall are continuous wiring structures.
  3. In claim 1, the via is a wiring structure that overlaps in a vertical direction perpendicular to the upper surface of the substrate and one end of the first wiring adjacent to the first sidewall of the interlayer insulating film in the first direction.
  4. A wiring structure according to claim 1, wherein the first length in the first direction from the first centerline extending in a vertical direction perpendicular to the upper surface of the substrate and penetrating the center of gravity of the first wiring to the first side wall decreases as it moves away in the vertical direction from the upper surface of the substrate at a height corresponding to the first lower part of the first side wall, and increases as it moves away in the vertical direction from the upper surface of the substrate at a height corresponding to the first upper part of the first side wall.
  5. A wiring structure according to claim 1, wherein the second length in the first direction from the second centerline extending in a vertical direction perpendicular to the upper surface of the substrate and penetrating the center of gravity of the second wiring to the second side wall increases as it moves away from the upper surface of the substrate in the vertical direction, and the rate of increase of the second length at a height corresponding to the second upper part of the second side wall is greater than the rate of increase of the second length at a height corresponding to the second central part of the second side wall.
  6. In claim 1, the second side wall is a wiring structure comprising a pointed point disposed between the second central part and the second upper part.
  7. In claim 1, the side walls in the second direction parallel to the upper surface of the substrate of the first and second wirings and intersecting the first direction include a pointed point.
  8. A first interlayer insulating film and vias accommodated therein are formed on a substrate; A second interlayer insulating film is formed on the first interlayer insulating film; A hard mask is formed on the second interlayer insulating film, comprising a first opening extending by a first length in a first direction parallel to the upper surface of the substrate, and a second opening spaced apart from the first opening in the first direction and extending by a second length smaller than the first length in the first direction; By etching the second interlayer insulating film using the hard mask, the first opening and the second opening are expanded into the second interlayer insulating film in a vertical direction perpendicular to the upper surface of the substrate; An ion beam etching process is performed to etch the sidewalls of the first opening and the upper sidewalls of the second opening; and A method for manufacturing a wiring structure in which a first wiring and a second wiring are formed respectively within the first and second openings.
  9. A method for manufacturing a wiring structure according to claim 8, wherein the etching rate for the lower sidewall of the first opening during the ion beam etching process is greater than the etching rate for the upper sidewall of the first opening.
  10. A method for manufacturing a wiring structure according to claim 8, wherein in the ion beam etching process, the ion beam is blocked by the hard mask so that the lower sidewall of the second opening is not exposed to the ion beam.

Description

Wiring structures and methods of manufacturing the same The present invention relates to a wiring structure and a method for manufacturing the same. As semiconductor devices containing wiring structures become highly integrated, the pitch of the wiring is decreasing, and the development of patterning processes to implement this is necessary. FIGS. 1 to 3 are plan and cross-sectional views for illustrating wiring structures according to exemplary embodiments. FIGS. 4 to 10 are cross-sectional views illustrating a method for manufacturing a wiring structure according to exemplary embodiments. FIG. 11 is a cross-sectional view illustrating a wiring structure according to exemplary embodiments. Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. In the following detailed description of the invention (excluding claims), two directions that intersect each other among the horizontal directions parallel to the upper surface of the substrate are defined as the first and second directions (D1, D2), respectively, and a vertical direction perpendicular to the upper surface of the substrate is defined as the third direction (D3). In exemplary embodiments, the first and second directions (D1, D2) may be orthogonal to each other. [Example] FIGS. 1 to 3 are plan and cross-sectional views for illustrating wiring structures according to exemplary embodiments. FIG. 1 is a plan view, FIG. 2 is a cross-sectional view of FIG. 1 taken along line A-A', and FIG. 3 is a cross-sectional view of FIG. 1 taken along line B-B'. Referring to FIGS. 1 to 3, the wiring structure may include a substrate (100), transistors (110), vias (320), first, second, and third wirings (420, 440, 460), first, second, and third interlayer insulating films (200, 300, 400), and an etch stop film (390). The substrate (100) may include, for example, a semiconductor material such as silicon, germanium, silicon-germanium, etc., or a Group III-V compound such as GaP, GaAs, GaSb, etc. According to some embodiments, the substrate (100) may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. The transistors (110) may be disposed on the upper surface of the substrate (100) and may be disposed spaced apart from each other in a horizontal direction parallel to the upper surface of the substrate (100). In exemplary embodiments, the transistor (110) may include a gate structure and a source/drain region disposed on the upper surface of the substrate (100) adjacent thereto. Only one of the plurality of transistors (110) is illustrated exemplarily in the drawing. Meanwhile, in addition to transistors (110), other active or passive components may be placed on the substrate (100). The first and second interlayer insulating films (200, 300), the etch stop film (390), and the third interlayer insulating film (400) can be sequentially stacked on the substrate (100). The first interlayer insulating film (200) can cover transistors (110) disposed on the upper surface of the substrate (100). Each of the first to third interlayer insulating films (200, 300, 400) may include an oxide, for example, silicon oxide. The etch stop film (390) may include an insulating nitride, for example, aluminum nitride. The via (320) can be accommodated within the second interlayer insulating film (300). The first to third wires (420, 440, 460) can be accommodated within the third interlayer insulating film (400). The first wire (420) and the second wire (440) can be aligned with each other in the first direction (D1). The third wire (460) can be spaced apart from each of the first and second wires (420, 44) in the second direction (D2). The first wire (420) can penetrate the third interlayer insulating film (400) and the etch stop film (390) to contact the upper surface of the via (320). The first wiring (420) may have a first length in the first direction (D1), the second wiring (440) may have a second length in the first direction (D1), and the third wiring (460) may have a third length in the first direction (D1). At this time, the third length may be greater than the first length, and the first length may be greater than the second length. For convenience of explanation, the portion of the third interlayer insulating film (400) interposed between the first and second wires (420, 440) will be referred to as the first portion (400a) below. At this time, the first portion (400a) of the third interlayer insulating film (400) may have a first sidewall (S1) and a third sidewall (S3) in the first direction (D1). The first sidewall (S1) may be in contact with one sidewall in the first direction (D1) of the first wire (420), and the third sidewall (S3) may be in contact with one sidewall in the first direction (D1) of the second wire (440). The one sidewall in the first direction (D1) of the first wire (420) and the one sidewall in the first direction (D1) of the second wire (440) may face