KR-20260063258-A - SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

Abstract

A semiconductor package according to the present invention comprises a substructure, a processor chip, a memory chip, and an optical chip on the substructure, and a leveling structure and an optical structure on the optical chip, wherein the substructure comprises an integrated circuit structure connecting the processor chip and the optical chip, and a bridge structure spaced apart from the integrated circuit structure and connecting the memory chip and the processor chip, wherein the level of the upper surface of the leveling structure is the same as the level of the upper surface of the memory chip, and the leveling structure and the optical structure are spaced apart.

Inventors

• 황현정
• 강정훈

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20241030

Claims (10)

1. Substructure; A processor chip, a memory chip, and an optical chip on the above-mentioned substructure; and Includes a leveling structure and an optical structure on the above optical chip, The above substructure is, An integrated circuit structure connecting the processor chip and the optical chip, and It includes a bridge structure that is spaced apart from the integrated circuit structure and connects the memory chip and the processor chip, The level of the upper surface of the leveling structure is the same as the level of the upper surface of the memory chip, and A semiconductor package in which the leveling structure and the optical structure are spaced apart.
2. In Article 1, The above optical chip and the above optical structure are bonded with an optical adhesive, The above optical adhesive comprises at least one of acrylic or epoxy, for a semiconductor package.
3. In Article 1, The above integrated circuit structure includes a plurality of through-vias, and A semiconductor package in which the plurality of through-vias of the integrated circuit structure are connected to the processor chip.
4. In Article 1, A semiconductor package having bumps interposed between the integrated circuit structure and the optical chip, and between the integrated circuit structure and the processor chip, respectively.
5. In Article 1, The above leveling structure is a semiconductor package comprising silicon.
6. In Article 1, The optical chip includes an optical circuit layer in contact with the leveling structure, and The above optical circuit layer includes a circuit step section, and A semiconductor package comprising a step layer of the optical structure offset from the circuit step section, the above optical structure.
7. In Article 1, A molding film is interposed between the memory chip and the processor chip, and A molding film is interposed between the leveling structure and the processor chip, and A semiconductor package in which the side wall of the leveling structure facing the optical structure is exposed.
8. In Article 7, Width of the above optical chip A semiconductor package in which the shortest distance from the sidewall of the optical chip in contact with the molding film to the outermost sidewall of the optical structure is greater.
9. In Article 1, The above bridge structure is, A plurality of bridge pads in contact with the processor chip and the memory chip, and A semiconductor package comprising a bridge wiring connecting a bridge pad in contact with the processor chip and a bridge pad in contact with the memory chip.
10. Substructure; A processor chip, a memory chip, and an optical chip on the above-mentioned substructure; and Includes a leveling structure and an optical structure on the above optical chip, The above substructure includes an integrated circuit structure connecting the processor chip and the optical chip, and The level of the upper surface of the leveling structure is the same as the level of the upper surface of the optical structure, and The leveling structure and the light structure are spaced apart, A semiconductor package in which the sidewall of the optical structure facing the leveling structure is exposed.

Description

Semiconductor Package and Method for Manufacturing the Same The present invention relates to a semiconductor package and a method for manufacturing the same, and more specifically, to a semiconductor package including an integrated circuit and a method for manufacturing the same. A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. Typically, semiconductor packages involve mounting semiconductor chips on a printed circuit board and electrically connecting them using bonding wires or bumps. With the advancement of the electronics industry, various studies are underway to improve the reliability, increase integration, and miniaturize semiconductor packages. With the development of the electronics industry, there is an increasing demand for high functionality, high speed, and miniaturization of electronic components. In response to this trend, recent packaging technology is moving toward integrating multiple semiconductor chips within a single package. Recently, the demand for portable devices in the electronics market has been rapidly increasing, leading to a continuous demand for the miniaturization and lightweighting of electronic components mounted on these products. To achieve this miniaturization and lightweighting, not only is technology required to reduce the individual size of mounted components, but also semiconductor packaging technology to integrate multiple individual components into a single package. In particular, semiconductor packages handling high-frequency signals are required to achieve not only miniaturization but also superior electrical characteristics. FIGS. 1 and FIGS. 2 are cross-sectional views illustrating a semiconductor package according to embodiments of the present invention. FIG. 3 is a cross-sectional view illustrating a semiconductor package according to embodiments of the present invention. FIGS. 4a to 4h are cross-sectional views illustrating a method for manufacturing a semiconductor package according to embodiments of the present invention. A semiconductor package according to the concept of the present invention is described with reference to the drawings. FIGS. 1 and FIGS. 2 are cross-sectional views illustrating a semiconductor package according to embodiments of the present invention. Referring to FIGS. 1 and 2, a substructure (11) may be provided. The substructure (11) may have a plate shape extending along a plane extending in a first direction (D1) and a second direction (D2). The first direction (D1) and the second direction (D2) may intersect each other. For example, the first direction (D1) and the second direction (D2) may be horizontal directions that are orthogonal to each other. A memory chip (301), a processor chip (302), and an optical chip (303) may be provided on a substructure (11). A molding film (410) may be provided to surround the memory chip (301) and the processor chip (302). The molding film (410) may be interposed between the processor chip (302) and the optical chip (303). An optical structure (401) and a leveling structure (402) may be provided on the optical chip (303). The substructure (11), memory chip (301), processor chip (302), and optical chip (303) may be overlapped in a third direction (D3). The third direction (D3) may be a direction perpendicular to the first direction (D1) and the second direction (D2). The substructure (11), memory chip (301), processor chip (302), and optical chip (303) may be overlapped in a vertical direction. A solder pad (SP) may be provided under the lower structure (11). A solder ball (SB) may be connected to the solder pad (SP). Solder pads (SP) may include a conductive material. For example, solder pads (SP) may include copper (Cu). Solder balls (SB) may be provided on solder pads (SP). Through the solder balls (SB), the semiconductor package may be electrically connected to an external device. The solder balls (SB) may include a conductive material. The solder balls (SB) may include a solder material. The solder material may include, for example, tin, bismuth, lead, silver, or an alloy thereof. The substructure (11) may include an integrated circuit structure (102) connecting a processor chip (302) and an optical chip (303), a bridge structure (104) connecting a processor chip (302) and a memory chip (301), and a plurality of connection structures (101). The processor chip (302), the optical chip (303), and the memory chip (301) may be connected to corresponding connection structures (101), and the processor chip (302), the optical chip (303), and the memory chip (301) may be connected to solder balls (SB) through corresponding connection structures (101). The integrated circuit structure (102) and the bridge structure (104) may be separated. The integrated circuit structure (102) and the connection structure (101) may be separated. The bridge structure (104) and the connection structure (101) may be separated. The integrated circuit structu