KR-20260063364-A - PHASE DETECTION DEVICE AND METHOD FOR DETECTING PHASE

Abstract

A receiver according to one embodiment may include an analog front end that receives a data input/output signal and amplifies the data input/output signal to generate a processing signal; a time interleaved analog-digital converter (TI ADC) that samples the processing signal based on a plurality of clock signals and generates a plurality of digital data signals; a Muller-Muller phase detector that receives the plurality of digital data signals from the time interleaved analog-digital converter and drives at least one of a plurality of arithmetic units based on a transition between two digital data signals that are continuously received among the plurality of digital data signals; a monitoring circuit that receives the plurality of digital data signals from the time interleaved analog-digital converter and receives a multi-level signal transmitted from a transmitter, and generates a monitoring output signal based on the plurality of digital data signals and the multi-level signal; and a control logic that receives a monitoring output signal output from the monitoring circuit and generates a plurality of arithmetic unit selection signals that drive the plurality of arithmetic units based on the monitoring output signal.

Inventors

• 정진욱
• 박재우
• 곽명보
• 백승엽

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20241030

Claims (20)

1. An analog front end that receives a data input/output signal and amplifies the data input/output signal to generate a processing signal; A time-interleaved analog-digital converter (TI ADC) that samples the processing signal based on a plurality of clock signals and generates a plurality of digital data signals; A Muller-Muller phase detector that receives a plurality of digital data signals from the time-interleaved analog-to-digital converter and drives at least one of a plurality of arithmetic units based on a transition between two digital data signals that are continuously received among the plurality of digital data signals; A monitoring circuit that receives a plurality of digital data signals from the time-interleaved analog-to-digital converter, receives a multi-level signal transmitted from a transmitter, and generates a monitoring output signal based on the plurality of digital data signals and the multi-level signal; and Control logic that receives a monitoring output signal output from the above monitoring circuit and generates a plurality of arithmetic unit selection signals that drive the plurality of arithmetic units based on the monitoring output signal. A receiver including
2. In paragraph 1, The above-mentioned Muller-Muller phase detector is, A phase determination decoder that generates transition information for the two digital data signals, determines phase information for clock signals that sample the two digital data signals among the plurality of clock signals, and outputs a phase determination signal including the phase information; A plurality of arithmetic units that receive the phase determination signal and generate a plurality of sampling control signals that control the timing of the plurality of clock signals based on the phase determination signal; A plurality of switches connecting the above plurality of arithmetic units and voltage sources; and A plurality of multiplexers that receive the plurality of sampling control signals from the plurality of arithmetic units and selectively output the plurality of sampling control signals, receiving set.
3. In paragraph 2, The above-mentioned phase determination decoder is, Based on the above transition information, a first operation unit is selected among the plurality of operation units, and the phase determination signal is output to the first operation unit. The above plurality of switches are, Turned on or turned off based on the above plurality of operation unit selection signals, receiving set.
4. In paragraph 3, The above monitoring circuit is, Calculating a signal-to-noise ratio based on signal power measured through the squared mean of the voltage level values of the digital data signal or the multi-level signal, and noise power including power loss occurring in the transmission path, and generating the signal-to-noise ratio as the monitoring output signal. receiving set.
5. In paragraph 4, If the monitoring output signal is greater than or equal to a first reference value, based on the plurality of arithmetic unit selection signals, a first switch connected to the first arithmetic unit among the plurality of switches is turned off, and a first multiplexer connected to the first arithmetic unit among the plurality of multiplexers does not transmit the sampling control signal of the first arithmetic unit to a loop filter based on the plurality of arithmetic unit selection signals. receiving set.
6. In paragraph 4, If the monitoring output signal is less than a first reference value, a first switch connected to the first arithmetic unit is turned on based on the plurality of arithmetic unit selection signals, and the first multiplexer connected to the first arithmetic unit among the plurality of multiplexers outputs a sampling control signal of the first arithmetic unit based on the plurality of arithmetic unit selection signals. receiving set.
7. In paragraph 3, The above monitoring circuit is, Calculate a bit error rate based on the total number of transmission bits of the multi-level signal transmitted from the transmitter and the number of error bits between the multi-level signal and the digital data signal, and generate the calculated bit error rate as the monitoring output signal. receiving set.
8. In Paragraph 7, If the monitoring output signal is less than a first reference value, based on the plurality of arithmetic unit selection signals, the first switch connected to the first arithmetic unit among the plurality of switches is turned off, and the first multiplexer connected to the first arithmetic unit among the plurality of multiplexers does not transmit the sampling control signal of the first arithmetic unit to the loop filter based on the plurality of arithmetic unit selection signals. receiving set.
9. In paragraph 8, If the monitoring output signal is greater than or equal to a first reference value, the first switch is turned on based on the plurality of arithmetic unit selection signals, and the first multiplexer connected to the first arithmetic unit among the plurality of multiplexers outputs a sampling control signal of the first arithmetic unit based on the plurality of arithmetic unit selection signals. receiving set.
10. In paragraph 3, The above phase determination signal is, The above transition information; and The values of the two digital data signals above A receiver that further includes.
11. A plurality of arithmetic units that output a plurality of sampling control signals corresponding to the transition of two adjacent digital data signals and adjusting the sampling timing for sampling the signals; A monitoring circuit that acquires the digital data signal and receives a multi-level signal from a transmitter having one of N (N is a positive) signal levels, and generates a monitoring output signal using the digital data signal and the multi-level signal; Control logic that generates a plurality of operation unit selection signals for driving the plurality of operation units by comparing the above monitoring output signal with a first reference value; and A plurality of switches that transmit a driving voltage from a voltage source to the plurality of arithmetic units based on the plurality of arithmetic unit selection signals. A phase detection device including
12. In Paragraph 11, A plurality of multiplexers that selectively output the plurality of sampling control signals based on the plurality of arithmetic unit selection signals. A phase detection device further comprising
13. In Paragraph 12, The above monitoring output signal is, A signal including a signal representing a signal-to-noise ratio determined based on the signal power of the multi-level signal, the signal power of the digital data signal, and noise power including power loss occurring in the transmission path. Phase detection device.
14. In Paragraph 13, The above control logic generates a plurality of arithmetic unit selection signal that drives m (m is a positive integer) of the plurality of arithmetic units based on a monitoring output signal that is less than a first reference value, and Among the plurality of switches, the switches connected to the m arithmetic units are turned on based on the plurality of arithmetic unit selection signals, and Among the plurality of multiplexers, the multiplexers connected to the m arithmetic units output sampling control signals output from the m arithmetic units based on the arithmetic unit selection signal. Phase detection device.
15. In Paragraph 14, The control logic above generates a plurality of operation unit selection signals that drive n (a positive number such that n < m) of the plurality of operation units based on the monitoring output signal which is greater than or equal to the first reference value, and Among the plurality of switches, the switches connected to the n arithmetic units are turned off upon receiving the plurality of arithmetic unit selection signal, and Among the plurality of multiplexers, the multiplexers connected to the n arithmetic units do not transmit the sampling control signal output from the n arithmetic units to the loop filter. Phase detection device.
16. In Paragraph 12, The above monitoring output signal is, A signal indicating a bit error rate, determined based on the number of bit errors of the multi-level signal and the digital data signal, Phase detection device.
17. In Paragraph 13, The above control logic generates a plurality of operation unit selection signal that drives m (m is a positive integer) of the plurality of operation units based on the monitoring output signal that is greater than or equal to a first reference value, and Among the plurality of switches, the switches connected to the m arithmetic units are turned on based on the plurality of arithmetic unit selection signals, and Among the plurality of multiplexers, the multiplexers connected to the m arithmetic units output sampling control signals output from the m arithmetic units based on the arithmetic unit selection signal. Phase detection device.
18. In Paragraph 17, The above control logic generates a plurality of arithmetic unit selection signal for driving n (a positive number such that n < m) of the plurality of arithmetic units based on the monitoring output signal which is less than the first reference value, and Among the plurality of switches, the switches connected to the n arithmetic units are turned off upon receiving the plurality of arithmetic unit selection signal, and Among the plurality of multiplexers, the multiplexers connected to the n arithmetic units do not transmit the sampling control signal output from the n arithmetic units to the loop filter. Phase detection device.
19. A step of calculating a bit error rate based on a multi-level signal having one signal level among N (N is a positive number) signal levels received from a transmitter and a digital data signal obtained from a time-interleaved analog-to-digital converter; A step of comparing the above-mentioned calculated bit error rate with a first reference value, and generating a plurality of arithmetic unit selection signals to turn on or turn off a plurality of switches respectively connected between a plurality of arithmetic units and voltage sources based on the result of the comparison; and A step of providing the plurality of arithmetic unit selection signals to the plurality of multiplexers that receive the plurality of switches and the sampling control signals output from the plurality of arithmetic units. A phase detection method including
20. In Paragraph 19, The step of generating the above plurality of operation unit selection signals is, A phase detection method comprising the step of generating a plurality of arithmetic unit selection signals to turn on the plurality of switches when the bit error rate is greater than or equal to a first reference value, and generating a plurality of arithmetic unit selection signals to turn off the plurality of switches when the bit error rate is less than the first reference value.

Description

Phase Detection Device and Phase Detection Method The present disclosure relates to a phase detection device and a phase detection method for detecting a phase difference between a data signal and a clock signal. While electronic devices operate internally through digital signal processing, their interfaces with external devices rely primarily on analog signal transmission. As the performance of electronic devices improves, communication frequencies are becoming increasingly higher; consequently, the impact of jitter in signals received from external devices can become more pronounced. Due to the effects of jitter, timing mismatches may occur when the receiver samples analog signals into digital format. This timing instability can lead to bit errors and sampling distortion during the signal conversion process. Consequently, the integrity of the analog signals received by the receiver from external devices may be compromised. FIG. 1 is a block diagram of a memory system according to one embodiment. FIG. 2 is a block diagram showing a memory device according to one embodiment. FIGS. 3 and 4 are block diagrams showing a transmitter and a receiver included in each of the memory controller and memory device according to one embodiment. FIG. 5 is a block diagram of a data transmission and reception system according to one embodiment. FIG. 6 is a graph showing a processing signal according to one embodiment. FIG. 7 is a circuit diagram showing a time-interleaved analog-to-digital converter according to one embodiment. Figure 8 is a graph showing the process of a processing signal being converted into digital data through an analog-to-digital converter. FIG. 9 is a block diagram showing a partial configuration of a Müller-Müller phase detector according to one embodiment. FIG. 10 is a flowchart illustrating the process of driving an arithmetic unit and a multiplexer by an arithmetic unit selection signal according to one embodiment. Figure 11 is a table showing the gain and current consumption generated in a Müller-Müller phase detector based on the transition of digital data. FIG. 12 is an exemplary block diagram showing a computer device according to one embodiment. Embodiments of the present invention are described below with reference to the attached drawings so that those skilled in the art can easily implement them. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. In addition, to clearly explain the invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification have been given similar reference numerals. In the flowcharts described with reference to the drawings, the order of operations may be changed, multiple operations may be merged or divided, and certain operations may not be performed. Additionally, expressions written in the singular form may be interpreted as singular or plural unless explicit expressions such as "one" or "singular" are used. Terms including ordinal numbers, such as the first, the second, etc., may be used to describe various components, but the components are not limited by these terms. These terms may be used for the purpose of distinguishing one component from another. The present disclosure will be explained in more detail below through examples. These examples are merely for illustrating the present disclosure and do not limit the scope of protection of the rights of the present disclosure. FIG. 1 is a block diagram of a memory system according to one embodiment. Referring to FIG. 1, the memory system (100) includes a memory device (110) and a memory controller (120). In some embodiments, the memory device (110) and the memory controller (120) are connected through a memory interface and can exchange signals through the memory interface. A memory device (110) includes a memory cell array (111) and a data input/output circuit (112). The memory cell array (111) includes a plurality of memory cells connected in a plurality of rows and a plurality of columns. In some embodiments, the rows may be defined by word lines and the columns may be defined by bit lines. The data I/O circuit (112) may store data transmitted from the outside in the memory cell array (111) or output data stored in the memory cell array (111) to the outside of the memory device (110) (i.e., a memory controller (120), etc.). The data I/O circuit (112) may include a transmitter (113) and a receiver (114). The transmitter (113) may receive data (DATA) from the memory cell array (111), encode it, and output a data input/output signal (DQ) based on the encoded signal. In one embodiment, a multi-symbol (or multi-level) modulation scheme may be used to modulate a signal communicated between the memory controller (120) and the memory device (110). Examples of multi-symbol modulation schemes include, but are not limited to, pulse amplitude modulation (PAM), quadrature amplitude