KR-20260063386-A - Semiconductor Device Having Hybrid Memory Layers and Method of Manufacturing the Same

Abstract

A semiconductor device is described comprising: a first wiring line extending in a first direction; a second wiring line extending in a second direction; and a memory cell disposed between the first wiring line and the second wiring line. The memory cell comprises: a first electrode; a first memory layer comprising a ferroelectric layer; a second electrode; a second memory layer comprising a high dielectric layer; an oxygen reservoir layer; and a third electrode.

Inventors

• 구원태

Assignees

• 에스케이하이닉스 주식회사

Dates

Publication Date

20260507

Application Date

20241030

Claims (20)

1. A first wiring line extending in the first direction; A second wiring line extending in a second direction; and It includes a memory cell disposed between the first wiring line and the second wiring line, and The above memory cell is: First electrode; A first memory layer including a ferroelectric layer; Second electrode; A second memory layer including a high dielectric layer; Oxygen reservoir layer; and A semiconductor device including a third electrode.
2. In paragraph 1, The first electrode above is a semiconductor device comprising a polycrystalline silicon layer.
3. In paragraph 1, The first memory layer is a semiconductor device comprising a crystalline hafnium zirconium oxide layer.
4. In paragraph 1, The above second electrode is a semiconductor device comprising a titanium layer.
5. In paragraph 1, The above second memory layer is a semiconductor device comprising an amorphous hafnium oxide layer.
6. In paragraph 1, The above second memory layer is a semiconductor device comprising oxygen vacancy.
7. In paragraph 1, The above oxygen reservoir layer is a semiconductor device comprising a titanium oxide layer.
8. In paragraph 1, The above third electrode is a semiconductor device comprising a titanium layer.
9. In paragraph 1, A semiconductor device further comprising a first contact plug between the first wiring line and the memory cell.
10. In paragraph 1, A semiconductor device further comprising a second contact plug between the memory cell and the second wiring line.
11. In paragraph 1, A semiconductor device in which the first direction and the second direction are perpendicular to each other.
12. In paragraph 1, The first memory layer is disposed on the first electrode, and The second electrode is disposed on the first memory layer, and The second memory layer is disposed on the second electrode, and The oxygen reservoir layer is disposed on the second memory layer, and The third electrode is a semiconductor device disposed on the oxygen reservoir layer.
13. A first electrode material layer is formed, and An interface insulating material layer is formed on the first electrode material layer, and A first memory material layer is formed on the above interface insulating material layer, and A second electrode material layer is formed on the first memory material layer, and A second memory material layer is formed on the second electrode material layer, and A third electrode material layer is formed on the second memory material layer, and A method for manufacturing a semiconductor device comprising performing an oxygen scavenging process to eliminate the interface insulating layer and forming a metal oxide layer between the second electrode material layer and the third electrode material layer.
14. In Paragraph 13, A method for manufacturing a semiconductor device in which the first electrode material layer comprises a polycrystalline silicon layer.
15. In Paragraph 13, A method for manufacturing a semiconductor device in which the above-mentioned interface insulating material layer comprises silicon oxide.
16. In paragraph 15, A method for manufacturing a semiconductor device comprising forming the above-mentioned interface insulating material layer by oxidizing the upper surface of the above-mentioned first electrode material layer.
17. In Paragraph 13, A method for manufacturing a semiconductor device in which the ferroelectric layer comprises a crystalline hafnium zirconium oxide layer.
18. In Paragraph 13, The above second electrode is a method for manufacturing a semiconductor device comprising titanium.
19. In Paragraph 13, A method for manufacturing a semiconductor device in which the first memory material layer comprises an amorphous hafnium oxide layer.
20. In Paragraph 13, A method for manufacturing a semiconductor device in which the metal oxide layer comprises a titanium oxide layer.

Description

Semiconductor Device Having Hybrid Memory Layers and Method of Manufacturing the Same The present disclosure relates to a semiconductor device and a method for manufacturing the same, and in particular to a semiconductor device having hybrid memory layers and a method for manufacturing the same. Semiconductor devices with ferroelectric layers are being researched. Since ferroelectric layers have low on-current characteristics, power consumption is low. However, practical application is difficult because the on-current is very low and the on/off current ratio is insufficient. FIGS. 1a and 1b are a circuit diagram and a perspective view schematically showing a cell array structure of a semiconductor device according to one embodiment of the present disclosure. FIG. 2a is a circuit diagram schematically showing a cell array structure of a semiconductor device according to one embodiment of the present disclosure, and FIG. 2b is a cross-sectional view schematically showing a unit cell of a semiconductor device according to one embodiment of the present disclosure. FIG. 3 is a cross-sectional view schematically showing the memory cell structure of a semiconductor device according to one embodiment of the present disclosure. FIGS. 4a to 4e are schematic cross-sectional views showing a method for forming a memory cell according to one embodiment of the present disclosure. The embodiments described in this disclosure are described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustrate the concepts described in this disclosure. Examples or embodiments according to the technical spirit of this disclosure may be carried out in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this disclosure. Hatching throughout the drawing indicates corresponding or similar areas between the drawings rather than indicating materials related to each area. If one component is defined as being "connected" or "interlocked" to another component, the components may be connected or interlocked directly or through another component interposed between them. If two components are identified as being "directly connected" or "directly interlocked," one component is directly connected or directly interlocked to the other component without any other component interposed between them. If one component is defined as being "above," "up," "below," or "below" another component, the components may come into direct contact with each other, or another component may be interposed between the components. Other terms implying relative spatial relationships or directions, such as "vertical," "horizontal," "top," "top," "bottom," "floor," "upper," "lower," "lower," "bottom," "top," "upper," "side," "flat," "high," "topmost," "lower," "bottommost," "front," "back," "left," "right," "column," "row," "level," "level," "water level," and others, are used solely for ease of explanation or for reference to the drawings and are not otherwise limited. Other spatial relationships or directions not shown in the drawings or described herein are possible within the scope of this disclosure. Terms such as "first" and "second" are used to distinguish various elements and do not imply the size, order, priority, quantity, or importance of the elements. In one example, the first component may be named as the second component, and the second component may be named as the first component in another example. In the description, if a component included in one embodiment is described in a singular form, the component may be interpreted as including a plurality of components that perform the same or similar functions. Technical concepts are disclosed together with the examples and embodiments described above. Those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and technical concepts of this disclosure. The embodiments disclosed herein should be considered in an illustrative rather than a restrictive sense. Accordingly, the scope of this disclosure is not limited to the descriptions above. All modifications within the meaning and scope of the equivalence of the claims are included within that scope. FIGS. 1a and 1b are a schematic diagram and a perspective view, respectively, showing a cell array structure (CA1) of a semiconductor device according to one embodiment of the present disclosure. Referring to FIGS. 1a and 1b, the cell array structure (CA1) of a semiconductor device according to one embodiment of the present disclosure may include first wiring lines (10), second wiring lines (90), and memory cells (MC). The first wiring lines (10) may extend parallel to each other in a first horizontal direction (X). For example, the first wiring lines (10) may be word lines. The second wiring lines (90) may extend parallel to each other in