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KR-20260063406-A - SEMICONDUCTOR PACKAGE

KR20260063406AKR 20260063406 AKR20260063406 AKR 20260063406AKR-20260063406-A

Abstract

One embodiment of the present invention provides a semiconductor package comprising: a substrate including wiring; a chip stack including a plurality of semiconductor chips stacked on the substrate, wherein each of the plurality of semiconductor chips includes opposite upper and lower surfaces, opposite front and rear surfaces, opposite left and right surfaces, and connection pads disposed on the upper surface adjacent to the front surface; bonding wires electrically connecting the connection pads to the wiring of the substrate; a plurality of adhesive films disposed on the lower surface of each of the plurality of semiconductor chips; a mold layer covering the chip stack and the bonding wires; and connection bumps disposed below the substrate and electrically connected to the wiring, wherein at least one of the plurality of adhesive films covers the rear surface of at least one of the plurality of semiconductor chips.

Inventors

  • 추교수
  • 이광용
  • 허광회
  • 김무성
  • 정연욱

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260507
Application Date
20241030

Claims (10)

  1. A substrate including wiring; A chip stack comprising a plurality of semiconductor chips stacked on the substrate, wherein each of the plurality of semiconductor chips includes opposite upper and lower surfaces, opposite front and rear surfaces, opposite left and right surfaces, and connection pads disposed on the upper surface adjacent to the front surface; Bonding wires that electrically connect the above connection pads to the wiring of the above substrate; A plurality of attachment films disposed on the lower surface of each of the plurality of semiconductor chips; A mold layer covering the above chip stack and the above bonding wires; and It includes connection bumps disposed below the substrate and electrically connected to the wiring, and At least one of the plurality of attachment films is a semiconductor package that covers the rear side of at least one semiconductor chip among the plurality of semiconductor chips.
  2. In Article 1, The plurality of semiconductor chips are offset in a direction toward the rear side so that the connection pads are exposed in a vertical direction, and A semiconductor package comprising at least one attachment film, the attachment portion in contact with the lower surface of a corresponding semiconductor chip among the plurality of semiconductor chips, and a bending portion in contact with the rear surface of the at least one semiconductor chip.
  3. In Article 1, The plurality of semiconductor chips includes an upper semiconductor chip and at least one intermediate semiconductor chip disposed between the substrate and the upper semiconductor chip, and A semiconductor package comprising a plurality of adhesive films, a top adhesive film disposed on the lower surface of the top semiconductor chip, and at least one intermediate adhesive film disposed on the lower surface of each of the at least one intermediate semiconductor chip.
  4. In Paragraph 3, The upper attachment film above is, An attachment portion in contact with the lower surface of the upper semiconductor chip, and A semiconductor package comprising a lower surface of the attachment portion, a rear side surface of the at least one intermediate semiconductor chip, and a bending portion in contact with the lower surface of the at least one intermediate attachment film.
  5. In Paragraph 4, The above-mentioned bending portion of the upper attachment film further contacts the upper surface of the substrate in a semiconductor package.
  6. In Paragraph 4, A semiconductor package comprising at least one intermediate adhesive film, the adhesive portion in contact with the lower surface of the at least one intermediate semiconductor chip, and a bending portion in contact with at least one of the front side, the left side, and the right side of the at least one intermediate semiconductor chip.
  7. Substrate; At least one chip stack comprising a plurality of semiconductor chips stacked on the substrate, wherein each of the plurality of semiconductor chips includes a front side and a rear side opposite in a first direction, and a left side and a right side opposite in a second direction intersecting the first direction; Bonding wires that electrically connect the plurality of semiconductor chips above to the substrate; and It includes a plurality of attachment films each disposed below a corresponding semiconductor chip among the plurality of semiconductor chips above, and At least one of the plurality of attachment films has a first length in the first direction and a second length in the second direction, and The semiconductor chip corresponding to the above at least one attachment film has a first width in the first direction and a second width in the second direction, A semiconductor package in which at least one of the first length and the second length is larger than at least one of the first width and the second width.
  8. Substrate; A first chip stack disposed on the substrate and comprising a first upper semiconductor chip and a first intermediate semiconductor chip between the substrate and the first upper semiconductor chip; Bonding wires electrically connecting the first upper semiconductor chip and the first intermediate semiconductor chip to the substrate; A first top attachment film disposed below the first top semiconductor chip; and It includes a first intermediate attachment film disposed below the first intermediate semiconductor chip, and A semiconductor package in which the length in the first direction of the first upper attachment film is greater than the width in the first direction of the first upper semiconductor chip.
  9. In Article 8, The first upper attachment film is a semiconductor package that contacts at least one of the rear sides of each of the first upper semiconductor chip and the first intermediate semiconductor chip facing the first direction.
  10. In Article 8, A second chip stack disposed on the first chip stack and comprising a second upper semiconductor chip and a second intermediate semiconductor chip between the first chip stack and the second upper semiconductor chip; A second upper attachment film disposed below the second upper semiconductor chip; and It further includes a second intermediate attachment film disposed below the second intermediate semiconductor chip, and A semiconductor package in which the length in the first direction of the second upper attachment film is greater than the width in the first direction of the second upper semiconductor chip.

Description

Semiconductor Package {SEMICONDUCTOR PACKAGE} The present invention relates to a semiconductor package. With the miniaturization and increased performance of electronic devices, the development of highly integrated semiconductor chips is required. The increased heat generation from miniaturized and highly integrated semiconductor chips is a cause of performance degradation. Accordingly, semiconductor packaging technology capable of effectively dissipating the heat generated by semiconductor chips is required. FIG. 1a is a perspective view of a semiconductor package according to an exemplary embodiment, and FIG. 1b is a cross-sectional view taken along line I-I' of FIG. 1a. FIG. 2 is a perspective view of a semiconductor package according to an exemplary embodiment. FIG. 3 is a perspective view of a semiconductor package according to an exemplary embodiment. FIG. 4 is a perspective view of a semiconductor package according to an exemplary embodiment. FIG. 5a is a perspective view of a semiconductor package according to an exemplary embodiment, and FIG. 5b is a plan view of an intermediate semiconductor chip shown in FIG. 5a. FIG. 6 is a perspective view of a semiconductor package according to an exemplary embodiment. FIG. 7 is a side cross-sectional view of a semiconductor package according to an exemplary embodiment. FIGS. 8a to 8c are drawings for explaining the manufacturing process of an attachment film including a bending portion. FIGS. 9a to 9c are drawings for explaining the manufacturing process of the semiconductor package of FIG. 1a. FIGS. 10a to 10c are drawings for explaining the manufacturing process of the semiconductor package of FIG. 5a. Hereinafter, preferred embodiments of the present invention are described as follows with reference to the attached drawings. Unless otherwise specifically stated, terms such as 'upper,' 'upper surface,' 'lower,' 'lower surface,' and 'side surface' in this specification are based on the drawings and may actually vary depending on the direction in which the components are arranged. Additionally, ordinal numbers such as "first," "second," "third," etc., may be used as labels for specific elements, steps, directions, etc., to distinguish various elements, steps, directions, etc. from one another. Terms not described in the specification using "first," "second," etc., may still be referred to as "first" or "second" in the claims. Furthermore, terms referenced by a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere by a different ordinal number (e.g., "second" in the specification or another claim). FIG. 1a is a perspective view of a semiconductor package (100A) according to an exemplary embodiment, and FIG. 1b is a cross-sectional view along line I-I' of FIG. 1a. Referring to FIGS. 1a and 1b, a semiconductor package (100A) of an exemplary embodiment may include a substrate (110), a plurality of semiconductor chips (120), and a plurality of attachment films (130). According to the embodiment, the semiconductor package (100A) may further include a mold (140). According to the exemplary embodiments, at least some of the attachment films (130) may be in contact with each other to effectively dissipate heat generated from the semiconductor chips (120). For example, at least one attachment film (e.g., '130b') among the plurality of attachment films (130) may form a heat dissipation path connected to one side (e.g., 'BS1') of at least one semiconductor chip (e.g., '120a') among the plurality of semiconductor chips (120) and/or the upper surface (110S) of the substrate (110), thereby improving the heat dissipation characteristics of the semiconductor package (100A). The substrate (110) may be a substrate for a semiconductor package including a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape wiring board, etc. For example, the substrate (110) may be a double-sided printed circuit board (double-sided PCB) or a multi-layer printed circuit board (multi-layer PCB). A substrate (110) may include bonding pads (112P1), bump pads (112P2), and wiring (112) that electrically connects them. Bonding pads (112P1) may be placed on the upper surface of the substrate (110), and bump pads (112P2) may be placed on the lower surface of the substrate (110). The bonding pads (112P1) and bump pads (112P2) may include at least one metal or an alloy composed of two or more metals selected from copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and carbon (C). Connecting bumps (115) may be disposed on the lower portion of the bump pads (112P2). The connecting bumps (115) may be electrically connected to the semiconductor chip (120) through the wiring (112). The connecting bumps (115) may include, for example, tin (Sn) or an alloy containing tin (Sn) (e.g., Sn-Ag-Cu). The connecting bumps (115) may be electrically co