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KR-20260063425-A - MULTI-STAGE MULTILEVEL DUAL BUCK INVERTER USING COUPLED INDUCTOR

KR20260063425AKR 20260063425 AKR20260063425 AKR 20260063425AKR-20260063425-A

Abstract

One embodiment provides a multi-stage multi-level dual-buck inverter comprising: an input capacitor section including a plurality of input capacitors connected in series; a first buck switch section that operates in a buck-type ON/OFF manner between the input capacitor section and a first output to form a current of a first polarity; a second buck switch section that operates in a buck-type ON/OFF manner between the input capacitor section and a second output to form a current of a second polarity opposite to the first polarity; N (N is a natural number greater than or equal to 2) unit cells, wherein the first limiting inductor and the second limiting inductor are commonly connected to the cell outputs; and an output inductor connected to the outputs of the unit cells connected in a cascade, wherein the first limiting inductors of the N unit cells have the form of a first coupling inductor sharing a single core.

Inventors

  • 김상훈
  • 성윤동
  • 김혜진
  • 배국열
  • 윤기환
  • 박재영
  • 강모세

Assignees

  • 한국에너지기술연구원

Dates

Publication Date
20260507
Application Date
20241030

Claims (15)

  1. An input capacitor section comprising a plurality of input capacitors connected in series; a first buck switch section that operates in a buck-type ON/OFF manner between the input capacitor section and a first output to form a current of a first polarity; a second buck switch section that operates in a buck-type ON/OFF manner between the input capacitor section and a second output to form a current of a second polarity opposite to the first polarity; N (N is a natural number greater than or equal to 2) unit cells comprising a first limiting inductor connected to the first output and a second limiting inductor connected to the second output, wherein the first limiting inductor and the second limiting inductor are commonly connected to a cell output; and It includes an output inductor connected to the output of the unit cells connected in a cascade, and A multi-stage multi-level dual-buck inverter in which the first limiting inductors of the N unit cells have the form of a first coupling inductor sharing a single core.
  2. In paragraph 1, A multi-stage multi-level dual-buck inverter in which the second limiting inductors of the N unit cells have the form of a second coupling inductor sharing a single core.
  3. In paragraph 2, A multi-stage multi-level dual-buck inverter in which the first coupling inductor and the second coupling inductor are manufactured with separate cores.
  4. In paragraph 3, The above-mentioned first coupling inductor and the above-mentioned second coupling inductor are made of a circular core, multi-stage multi-level dual buck inverter.
  5. In paragraph 4, A multi-stage multi-level dual-buck inverter in which the limiting inductors of each unit cell occupy the same circumferential length around the circumference of the above-mentioned circular core.
  6. In paragraph 1, A multi-stage multi-level dual-buck inverter in which the first buck switch operates on/off during the first half-cycle of the AC cycle formed in the cell output, and the second buck switch operates on/off during the second half-cycle excluding the first half-cycle.
  7. In paragraph 1, A multi-stage multi-level dual-buck inverter in which the cell output of the K-th unit cell (where K is a natural number greater than or equal to 2 and less than or equal to N) is connected to the midpoint of the input capacitors of the (K-1)-th unit cell.
  8. In paragraph 1, A multi-stage multi-level dual-buck inverter in which the inductance of the first limiting inductor of each of the N unit cells has a value within a preset margin range.
  9. In paragraph 1, A multi-stage multi-level dual-buck inverter in which, when the output current of the output inductor flows through the first limiting inductor, the output current does not flow through the second limiting inductor.
  10. In paragraph 1, The first buck switch sections of the above N unit cells are phase shift PWM (Pulse Width Modulation) controlled, multi-stage multi-level dual buck inverter.
  11. In Paragraph 10, A multi-stage multi-level dual-buck inverter in which each of the first buck switch sections of the above N unicells is controlled to have a phase difference of 360/N degrees.
  12. In paragraph 1. A multi-stage multi-level dual-buck inverter, wherein the first buck switch section comprises a first switch connected to the high-voltage terminal of the input capacitor section and a second switch connected to the low-voltage terminal of the input capacitor section, and the second switch is a diode.
  13. In Paragraph 12, A multi-stage multi-level dual-buck inverter, wherein the second buck switch section includes a third switch connected to the high-voltage terminal of the input capacitor section and a fourth switch connected to the low-voltage terminal of the input capacitor section, and the third switch is a diode.
  14. In Paragraph 13, A multi-stage multi-level dual-buck inverter in which the first output is formed at the contact between the first switch and the second switch, and the second output is formed at the contact between the third switch and the fourth switch.
  15. In paragraph 1, A multi-stage multi-level dual-buck inverter in which the same voltage is input to each unit cell.

Description

Multi-stage multi-level dual buck inverter using coupling inductor This embodiment relates to inverter technology for converting DC voltage into AC voltage. An inverter, which converts direct current voltage into alternating current voltage, is a device that converts DC (Direct Current) power into AC (Alternating Current) power in electronic devices. Since the direct current supplied from a DC source, such as a battery, flows in a constant direction, it cannot be directly used in devices that require alternating current, such as household or industrial electricity, where the voltage direction changes periodically. Inverters are used to convert this DC power into the required AC form. The basic operating principle of an inverter is to form an alternating current waveform by periodically reversing the direction of the current using switching elements. Typical inverter circuits utilize semiconductor devices such as transistors, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), and IGBTs (Insulated Gate Bipolar Transistors) as switching elements to generate an alternating voltage with a constant frequency and waveform. The switching elements modulate the input DC voltage into an AC waveform by rapidly switching between on and off states. At this point, the characteristics and frequency of the output waveform are determined by the modulation method, and the desired waveform is typically realized through Pulse Width Modulation (PWM). In inverters, technologies for improving Total Harmonic Distortion (THD) and enhancing efficiency are critical. THD represents the ratio of all harmonic components, excluding the fundamental frequency, to the inverter output voltage; low THD contributes to improving power quality and enhancing system stability. Harmonics generated in inverters primarily originate during the switching process; when these harmonics are transmitted to the load, they cause electrical losses and, particularly in loads such as motors, lead to overheating or reduced efficiency. Therefore, THD improvement technologies that minimize harmonics play an essential role in enhancing output quality. One method to improve THD is to control Pulse Width Modulation (PWM) at high speed. By using PWM, the switching frequency can be increased, bringing the output waveform closer to the fundamental frequency. High-speed PWM is particularly useful for suppressing harmonics in advanced inverters, such as multi-level inverters. Additionally, a multi-level structure allows for the generation of more precise alternating current (AC) waveforms by dividing the output voltage into smaller steps. Multi-level inverters tend to reduce harmonics as the number of output steps increases, which ultimately results in a lower THD. To improve inverter efficiency, technologies are employed to reduce losses in switching devices and optimize the energy conversion process. Inverters primarily utilize semiconductor devices such as transistors, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), and IGBTs (Insulated Gate Bipolar Transistors) as switching devices, and the loss characteristics of these devices vary depending on the switching frequency and voltage. For example, MOSFETs are advantageous for high-speed switching and are mainly used in high-frequency applications, exhibiting high efficiency in low-voltage regions. On the other hand, IGBTs are suitable for high-power systems as they enable stable operation at high voltages, but their switching speed is relatively slow. By designing inverter circuits that take these device characteristics into account, switching losses can be minimized and overall efficiency improved. Against this backdrop, technologies for cascade multilevel inverters have recently been presented in various studies. However, these technologies have faced problems such as increased inverter volume and higher manufacturing costs due to the use of multiple inductors. FIG. 1 is a configuration diagram of a multi-stage multi-level dual-buck inverter according to one embodiment. FIG. 2 is a diagram showing the main waveform of a first unit cell according to one embodiment. Figure 3 is a sample image of a first coupling inductor in which the first limiting inductors of four unit cells share a single core. Figure 4 is a diagram showing the winding configuration of limiting inductors of 16 unit cells. Figure 5 is a diagram showing the equivalent inductance when limiting inductors are made independently of each other. FIG. 6 is a diagram showing the equivalent inductance when limiting inductors according to one embodiment have the form of a coupled inductor. Figure 7 shows the output waveform of an inverter when the limiting inductors have the form of uncoupled inductors. Figure 8 shows the output waveform of an inverter when the limiting inductors have the form of a coupling inductor. Hereinafter, some embodiments of the present invention will be described in detail with reference to the exemplary drawings.