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KR-20260063438-A - Three-dimensional semiconductor memory device and electronic system including the same

KR20260063438AKR 20260063438 AKR20260063438 AKR 20260063438AKR-20260063438-A

Abstract

The present invention provides a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device of the present invention comprises a stacked structure including alternately stacked gate electrodes and insulating films on a substrate, a vertical channel pattern within a channel hole penetrating the stacked structure, an ion storage pattern on the side of the vertical channel pattern, an electrolyte pattern between the vertical channel pattern and the ion storage pattern, and ion absorption patterns between the vertical channel pattern and the electrolyte pattern, wherein each of the ion storage pattern and the electrolyte pattern extends in a vertical direction on the upper surface of the substrate, and the ion absorption patterns may be spaced apart from each other in the vertical direction.

Inventors

  • 최현묵

Assignees

  • 삼성전자주식회사

Dates

Publication Date
20260507
Application Date
20241030

Claims (10)

  1. A stacked structure comprising alternately stacked gate electrodes and insulating films on a substrate; A vertical channel pattern within a channel hole penetrating the above-mentioned stacked structure; Ion storage pattern on the side of the above vertical channel pattern; Electrolyte pattern between the vertical channel pattern and the ion storage pattern; and Includes ion absorption patterns between the vertical channel pattern and the electrolyte pattern, Each of the above ion storage pattern and the above electrolyte pattern extends in a direction perpendicular to the upper surface of the substrate, and The above ion absorption patterns are three-dimensional semiconductor memory devices spaced apart from each other in the vertical direction.
  2. In Article 1, A three-dimensional semiconductor memory device in which each of the above ion absorption patterns is located at the same level as the corresponding insulating films.
  3. In Article 1, From a planar perspective, each of the above ion absorption patterns is a three-dimensional semiconductor memory device surrounding the above vertical channel pattern.
  4. In Article 1, A three-dimensional semiconductor memory device in which at least a portion of the above electrolyte pattern is in contact with the above vertical channel pattern.
  5. In Article 1, The above electrolyte pattern includes oxygen deficiencies, and The above ion storage pattern includes oxygen ions, The above ion absorption patterns are a three-dimensional semiconductor memory device configured to absorb the oxygen ions.
  6. In Article 1, The above ion absorption patterns are a three-dimensional semiconductor memory device comprising at least one of Ti, Cd, and Co.
  7. In Article 1, A three-dimensional semiconductor memory device in which at least a portion of the above electrolyte pattern is in contact with the above ion absorption patterns.
  8. In Article 1, The above ion absorption patterns are a three-dimensional semiconductor memory device spaced apart from the gate electrodes in the vertical direction.
  9. A stacked structure comprising alternately stacked gate electrodes and insulating films on a substrate; A vertical channel pattern within a channel hole penetrating the above-mentioned stacked structure; Ion storage patterns on the side of the above vertical channel pattern; and The electrolyte pattern between the vertical channel pattern and the ion storage patterns, wherein The above ion storage patterns are spaced apart from each other in a direction perpendicular to the upper surface of the substrate in a three-dimensional semiconductor memory device.
  10. In Article 9, The above electrolyte pattern includes oxygen deficiencies, and The above ion storage patterns are three-dimensional semiconductor memory devices containing oxygen ions.

Description

Three-dimensional semiconductor memory device and electronic system including the same. The present invention relates to a three-dimensional semiconductor memory device, and more specifically, to a non-volatile three-dimensional semiconductor memory device including a vertical structure, a method for manufacturing the same, and an electronic system implementing the same. In electronic systems requiring data storage, there is a demand for semiconductor devices capable of storing high-capacity data. To increase data storage capacity while meeting the superior performance and low cost demands of consumers, it is necessary to increase the integration density of semiconductor devices. In the case of two-dimensional or planar semiconductor devices, integration density is primarily determined by the area occupied by a unit memory cell, and thus is significantly influenced by the level of fine pattern formation technology. However, since ultra-expensive equipment is required for pattern miniaturization, the integration density of two-dimensional semiconductor devices remains limited despite increasing. Accordingly, three-dimensional semiconductor memory devices equipped with memory cells arranged in three dimensions are being proposed. FIG. 1 is a schematic diagram illustrating an electronic system including a three-dimensional semiconductor memory device according to embodiments of the present invention. FIG. 2 is a schematic perspective view showing an electronic system including a three-dimensional semiconductor memory device according to embodiments of the present invention. FIGS. 3 and 4 are drawings for illustrating a semiconductor package including a three-dimensional semiconductor memory device according to embodiments of the present invention, and are cross-sectional views taken along line I-I' of FIG. 2. FIG. 5 is a plan view illustrating a three-dimensional semiconductor memory device according to embodiments of the present invention. FIGS. 6a and 6b are drawings for illustrating a three-dimensional semiconductor memory device according to embodiments of the present invention, and are cross-sections cut along the lines A-A' and B-B' of FIG. 5. FIG. 7a is a drawing for explaining a part of a three-dimensional semiconductor memory device according to one embodiment of the present invention, and is an enlarged view of the P1 region of FIG. 6a. Figure 7b is a plan view cut along the line C-C' of Figure 7a. FIGS. 8 and 9 are drawings for explaining a part of a three-dimensional semiconductor memory device according to embodiments of the present invention, and are enlarged drawings of the P1 region of FIG. 6a. FIG. 10a is a drawing for explaining a part of a three-dimensional semiconductor memory device according to one embodiment of the present invention, and is an enlarged view of the P1 region of FIG. 6a. Figure 10b is a plan view cut along the line D-D' of Figure 10a. FIG. 11 is a drawing for explaining a part of a three-dimensional semiconductor memory device according to an embodiment of the present invention, and is an enlarged view of the P1 region of FIG. 6a. FIG. 12 is a drawing for explaining a part of a three-dimensional semiconductor memory device according to one embodiment of the present invention, and is an enlarged view of the P2 region of FIG. 6a. FIG. 13 is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to one embodiment of the present invention. FIGS. 14a to 19b are drawings for explaining a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention. FIGS. 20a to 21b are drawings for explaining a method for manufacturing a three-dimensional semiconductor memory device according to an embodiment of the present invention. Hereinafter, embodiments of the present invention will be described with reference to the attached drawings. Throughout the entire specification, the same reference numerals may refer to the same components. FIG. 1 is a schematic diagram illustrating an electronic system including a three-dimensional semiconductor memory device according to embodiments of the present invention. Referring to FIG. 1, an electronic system (1000) according to embodiments of the present invention may include a three-dimensional semiconductor memory device (1100) and a controller (1200) electrically connected to the three-dimensional semiconductor memory device (1100). The electronic system (1000) may be a storage device or an electronic device including a storage device that includes the three-dimensional semiconductor memory device (1100). For example, the electronic system (1000) may be a solid state drive device (SSD), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device that includes the three-dimensional semiconductor memory device (1100). The three-dimensional semiconductor memory device (1100) may be provided in a plurality. The three-dim