KR-20260063440-A - METHOD FOR PREDICTION OF PROCESS DEFECTS

Abstract

The present disclosure relates to a method for predicting process defects. The method for predicting process defects includes receiving design data comprising a plurality of layout patterns corresponding to a plurality of layers of a semiconductor chip; dividing the design data into tile units and generating a plurality of height maps corresponding to a plurality of tile regions; and determining whether there is a process defect associated with a plurality of tile regions based on the plurality of height maps.

Inventors

• 박민철
• 권세갑
• 김상연
• 김예지
• 김성렬
• 김영구

Assignees

• 삼성전자주식회사

Dates

Publication Date

20260507

Application Date

20241030

Claims (20)

1. In a process defect prediction method performed by at least one processor, A step of receiving design data including a plurality of layout patterns corresponding to a plurality of layers of a semiconductor chip; The step of dividing the above design data into tile units and generating a plurality of height maps corresponding to a plurality of tile areas; and A step of determining whether there are process defects associated with the plurality of tile regions based on the plurality of height maps. A process defect prediction method including
2. In paragraph 1, The step of generating the above plurality of height maps is, A process defect prediction method comprising the step of dividing the design data into a plurality of tile regions using a window of a predetermined size.
3. In paragraph 1, The step of generating the above plurality of height maps is, A process defect prediction method comprising the step of generating a plurality of height maps corresponding to each of the plurality of tile regions by estimating the height value of each point within each tile region using a height map generation model.
4. In paragraph 3, A process defect prediction method in which the height map generation model is a machine learning model trained based on training design data and measurement data for a semiconductor device corresponding to the training design data.
5. In paragraph 1, The step of determining whether there is a process defect, above, is A step of generating a plurality of high-resolution height maps based on each of the above plurality of height maps; and A step of determining whether there are process defects associated with the plurality of tile regions based on the plurality of high-resolution height maps. A process defect prediction method including
6. In paragraph 5, The step of generating the above plurality of high-resolution height maps is, A process defect prediction method comprising the step of generating a plurality of high-resolution height maps using a sub-pixel shift technique based on the plurality of height maps.
7. In paragraph 5, The step of generating the above plurality of high-resolution height maps is, The method includes the step of generating a plurality of high-resolution height maps based on each of the plurality of height maps using a resolution conversion model. A process defect prediction method in which the above-mentioned resolution conversion model is a machine learning model trained based on a training dataset including low-resolution images and high-resolution images.
8. In paragraph 1, The step of determining whether there is a process defect, above, is A step of generating a plurality of high-resolution height maps based on each of the above plurality of height maps; A step of generating a plurality of 3D representations corresponding to each of the plurality of high-resolution height maps; and A step of determining whether there is a process defect associated with the plurality of tile regions based on the plurality of 3D representations generated above. A process defect prediction method including
9. In paragraph 1, The step of determining whether there is a process defect, above, is A step of performing a process simulation based on the surface shape of each tile region corresponding to the plurality of height maps using a process simulation model; and A step of determining a defect region that exceeds a predetermined critical range based on the changed surface shape of each tile region according to the result of the above process simulation. A process defect prediction method including
10. In Paragraph 9, The above process simulation includes a polishing process simulation, and The step of determining the above defect area is, A method for predicting process defects, comprising the step of determining whether the changed surface shape of each tile region corresponds to an over-polished state or an under-polished state as a result of performing the above-mentioned polishing process simulation, and determining a defect region.
11. In Paragraph 9, The step of determining the above defect area is, A step of determining a defect index associated with each tile area based on the changed surface shape of each tile area; and A step of determining whether there are process defects associated with each tile area based on a defect index associated with each tile area. A process defect prediction method including
12. In Paragraph 9, A process defect prediction method in which the above-mentioned process simulation model is a machine learning model learned based on a learning data set including process variable data and process result data.
13. In paragraph 1, A process defect prediction method further comprising the step of generating a process defect color map for the semiconductor chip using a relative defect index for process defects associated with each tile area.
14. In paragraph 1, A method for predicting process defects, further comprising the step of identifying a suspected layout pattern among a plurality of layout patterns that is presumed to cause the process defect, based on a tile area among the plurality of tile areas determined to have a process defect.
15. In paragraph 1, A method for predicting process defects, wherein the above design data includes layout patterns up to a predetermined process step during the entire manufacturing process for the semiconductor chip.
16. In a process defect prediction method performed by at least one processor, A step of receiving design data including a plurality of layout patterns corresponding to a plurality of layers of a semiconductor chip; A step of dividing the above design data into tile units and generating multiple height maps corresponding to multiple tile areas; A step of generating a plurality of 3D representations corresponding to each of the plurality of height maps; and A step of determining whether there is a process defect associated with the plurality of tile regions based on the plurality of 3D representations above. A process defect prediction method including
17. In Paragraph 16, The step of determining whether there is a process defect, above, is A step of performing a process simulation based on the surface shape of each tile region corresponding to the plurality of 3D representations using a process simulation model; and A step of determining a defect region that exceeds a predetermined critical range based on the changed surface shape of each tile region according to the result of the above process simulation. A process defect prediction method including
18. In Paragraph 16, A process defect prediction method further comprising the step of generating a process defect color map for the semiconductor chip using a relative defect index for process defects associated with each tile area.
19. In Paragraph 16, A method for predicting process defects, further comprising the step of identifying a suspected layout pattern among a plurality of layout patterns that is presumed to cause the process defect, based on a tile area among the plurality of tile areas determined to have a process defect.
20. In a process defect prediction method performed by at least one processor, A step of receiving design data including a plurality of layout patterns corresponding to a plurality of layers of a semiconductor chip; A step of dividing the above design data into a plurality of tile regions; A step of generating a plurality of height maps corresponding to each of the plurality of tile regions by estimating the height value of each point within each tile region; A step of generating a plurality of high-resolution height maps based on each of the above plurality of height maps; A step of generating a plurality of 3D representations based on each of the above plurality of high-resolution height maps; A step of performing a process simulation based on the surface shape of each tile region corresponding to the plurality of 3D representations above; and A step of determining a defect region that exceeds a predetermined critical range based on the changed surface shape of each tile region according to the result of the above process simulation. A process defect prediction method including

Description

Method for Predicting Process Defects The present invention relates to a method for predicting process defects, and more specifically, to a method for determining a specific region within design data that is predicted to cause defects in a semiconductor device manufacturing process. With the advancement of semiconductor device manufacturing processes, defects caused by height differences between patterns formed during the process are occurring frequently. In particular, height differences between patterns generated at specific process steps are often transferred to subsequent processes, leading to defects, and it is difficult to identify the root cause of these defects through measurement monitoring alone. Defects caused by height differences between patterns during the semiconductor manufacturing process directly affect yield, and yield is a critical factor determining product quality and manufacturing costs. Therefore, rapidly detecting defects resulting from height differences between patterns and effectively analyzing their causes is essential to maintain high yield and ensure a stable manufacturing process. The information described above is intended to enhance understanding of the background of the present invention and may include information that does not constitute prior art. FIG. 1 is a block diagram illustrating an example of a process defect prediction device according to one embodiment of the present disclosure. FIG. 2 is a block diagram illustrating an example of a method for predicting process defects using design data according to one embodiment of the present disclosure. FIG. 3 is a block diagram illustrating an example of a method for predicting process defects using design data according to another embodiment of the present disclosure. FIG. 4 is a block diagram illustrating an example of a method for predicting process defects using design data according to another embodiment of the present disclosure. FIG. 5 is a block diagram illustrating an example of a method for predicting process defects using design data according to another embodiment of the present disclosure. FIG. 6 is a drawing for explaining a method for generating height maps according to one embodiment of the present disclosure. FIG. 7 is a drawing for explaining a method for generating height maps according to one embodiment of the present disclosure. FIG. 8 is a drawing for explaining a method for generating high-resolution height maps according to one embodiment of the present disclosure. FIG. 9 is a drawing for explaining a method for generating high-resolution height maps according to one embodiment of the present disclosure. FIG. 10 is a drawing for explaining a method for generating high-resolution height maps according to one embodiment of the present disclosure. FIG. 11 is a drawing for explaining a method for generating 3D representations according to one embodiment of the present disclosure. FIG. 12 is a drawing for explaining a method for determining a defect area according to one embodiment of the present disclosure. FIG. 13 illustrates an example of a method for determining a defect area through the results of performing a process simulation for each tile area according to one embodiment of the present disclosure. FIG. 14 shows an example of a process defect color map including a defect region determined according to one embodiment of the present disclosure. FIG. 15 is a flowchart illustrating an example of a process defect prediction method according to one embodiment of the present disclosure. FIG. 16 is a flowchart illustrating an example of a process defect prediction method according to one embodiment of the present disclosure. FIG. 17 is a flowchart illustrating an example of a process defect prediction method according to one embodiment of the present disclosure. FIG. 18 is a block diagram illustrating an example of a process defect prediction system according to one embodiment of the present disclosure. Hereinafter, various embodiments of the present invention will be described with reference to FIGS. 1 through 18. Throughout the entire specification, the same reference numerals may refer to the same components. FIG. 1 is a block diagram illustrating an example of a process defect prediction device (10) according to one embodiment of the present disclosure. Referring to FIG. 1, a process defect prediction device (10) can determine defect regions (DR) where defects are presumed to occur due to height differences between layout patterns within the design data (LDD), based on design data (LDD). The design data (LDD) may include multiple layout patterns corresponding to multiple layers of a semiconductor chip. The layout patterns may include shape, placement, size, and thickness information of the patterns required at each layer formation stage of the semiconductor chip. The multiple layout patterns have a vertical relationship, and as a result, height differences may occur between the patterns included in