KR-20260063497-A - MULTI-CORE PROCESSOR AND METHOD OF OPERATION THEREOF

KR20260063497AKR 20260063497 AKR20260063497 AKR 20260063497AKR-20260063497-A

Abstract

A multi-core processor and a method of operating the multi-core processor are disclosed. A method of operating the multi-core processor according to one embodiment may include the steps of: a first core transmitting a read request for a cache line to a first cache corresponding to the first core; the first cache transmitting a timeout setting request to a directory in response to the read request; the directory transmitting a timeout setting request to a second cache corresponding to the second core; the second cache converting the state of the cache line of the second core to a shared state in response to the timeout setting request and transmitting a timeout setting response to the first cache and the directory; converting the state of the cache line of the directory and the state of the cache line of the first core to a shared state; and, when a predetermined time is reached, converting the state of the cache line of the directory and the state of the cache line of the first core to an invalid state.

Inventors

조재언
명노영

Assignees

삼성전자주식회사

Dates

Publication Date: 20260507
Application Date: 20241030

Claims (19)

In the operation method of a multi-core processor, A step in which a first core transmits a read request for a cache line to a first cache corresponding to the first core; The first cache above transmits a request to set a timeout sharing state to the directory in response to the read request; The above directory transmits the timeout shared state setting request to the second cache corresponding to the second core; The second cache converts the state of the cache line of the second core to a shared state in response to the timeout setting request, and transmits a shared acceptance response to the first cache and the directory; A step of converting the state of the cache line of the above directory and the state of the cache line of the above first core to the shared state; and A step of performing a timeout to convert the state of the cache line of the directory and the state of the cache line of the first core when a predetermined time is reached. A method of operation of a multi-core processor including
In paragraph 1, The step of performing the above timeout is A step of determining whether the first core and the directory each reach the predetermined time; and Based on the judgment that the above-determined time has been reached, the step of converting the state of the cache line of the above-determined directory to the above-determined exclusive state and converting the state of the cache line of the above-determined first core to the above-determined invalid state A method of operation of a multi-core processor including
In paragraph 2, The step of determining whether the above-mentioned predetermined time is reached A step of determining whether the predetermined time is reached using a real-time counter (RTC) included in the first core and the directory, respectively. A method of operation of a multi-core processor including
In paragraph 2, The above first core and the above directory are each It includes a deadline buffer that stores information about when a timeout occurs, and The step of determining whether the above-mentioned predetermined time is reached A step of comparing the real-time counter with the time information stored in the first pointer of the deadline buffer. A method of operation of a multi-core processor including
In paragraph 4, The above first core and the above directory are each It includes an address buffer that stores address information of the above cache line, and The step of performing the above timeout is When the above-determined time is reached, the step of converting the state of the cache line of the directory to the exclusive state by referring to the address information of the cache line in the address buffer and converting the state of the cache line of the first core to the invalid state. A method of operation of a multi-core processor including
In paragraph 5, The above deadline buffer is A method of operation of a multi-core processor including information on the number of cache lines that match information on the time when the above timeout occurs.
In paragraph 6, After converting the state of the above cache line to the above invalid state, The step of increasing the first pointer of the above deadline by one; and A step of updating the first pointer of the address buffer based on information regarding the number of the cache lines. A method of operation of a multi-core processor including
In paragraph 3, The step of determining whether the above-mentioned predetermined time is reached A step of obtaining initial time counter information corresponding to the time when the state of the cache line of the above directory and the state of the cache line of the above first core are converted to the shared state; A step of determining that the predetermined time has been reached when the initial time counter information satisfies a predetermined bit condition. A method of operation of a multi-core processor including
In paragraph 8, The step of determining that the above-mentioned predetermined time has been reached A step of determining that the predetermined time has been reached when, while specific bits of the real-time counter are maintained in the same state as the initial time counter information, another bit satisfies a certain condition. A method of operation of a multi-core processor including
A recording medium storing a computer program for executing a method according to any one of claims 1 to 9 in combination with hardware.
A first processing unit including a first core and a first cache; A second processing unit including a second core and a second cache; and directory Includes, The above first core is A read request for a cache line is transmitted to a first cache corresponding to the first core, and The first cache above transmits a timeout setting request to the directory in response to the read request, and The above directory transmits the above timeout setting request to the second cache, and In response to the timeout setting request, the second cache changes the state of the cache line of the second core to a shared state, and transmits the timeout setting response to the first cache and the directory. The above directory converts the state of the above cache line of the above directory to the above shared state, and The first core converts the state of the cache line of the first core to the shared state, and A multi-core processor in which, when a predetermined time is reached, the directory and the first core perform a timeout to change the state of the cache line.
In Paragraph 11, The above first core and the above directory are A multi-core processor that determines whether each of the above-determined time is reached, and based on the determination that the above-determined time has been reached, converts the state of the above-determined cache line of the directory to the above-determined exclusive state and converts the state of the above-determined cache line of the first core to the above-determined invalid state.
In Paragraph 12, The above first core and the above directory are A multi-core processor that determines whether the predetermined time is reached by using a real-time counter (RTC) included in the first core and the directory, respectively.
In Paragraph 12, The above first core and the above directory are A multi-core processor comprising a deadline buffer that stores information about the time when a timeout occurs, and a real-time counter that determines whether the predetermined time is reached by comparing the time information stored in the first pointer of the deadline buffer.
In Paragraph 14, The above first core and the above directory are A multi-core processor comprising an address buffer storing address information of the above cache line, and, when the above-determined time is reached, references the address information of the above cache line in the address buffer to convert the state of the above cache line of the above directory to the above-determined exclusive state and converts the state of the above cache line of the first core to the above-determined invalid state.
In paragraph 15, The above deadline buffer is A multi-core processor including information on the number of cache lines that match information on the time when the above timeout occurs.
In Paragraph 16, After converting the state of the above cache line to the above invalid state, The above deadline buffer is Increase the first pointer of the above deadline by one, The above address buffer is A multi-core processor that updates a first pointer of the address buffer based on information about the number of cache lines.
In Paragraph 13, The above first core and the above directory are Obtain initial time counter information corresponding to the time when the state of the cache line of the above directory and the state of the cache line of the above first core are converted to the shared state, and A multi-core processor that determines that the predetermined time has been reached when the initial time counter information satisfies a predetermined bit condition.
In Paragraph 18, The above first core and the above directory are A multi-core processor that determines that a predetermined time has been reached when another bit satisfies a certain condition while specific bits of the real-time counter are maintained in the same state as the initial time counter information.

Description

Multi-core processor and method of operation thereof Embodiments of the present invention relate to a multi-core processor and a method of operating the same. In modern computing environments, multicore processors are widely used and play a crucial role in maximizing performance through parallel processing. As these multicore processors share memory resources while processing tasks simultaneously, cache memory is attached to each core to manage this efficiently. While cache memory can improve overall system performance by increasing memory access speeds, maintaining cache consistency becomes a critical issue when data is shared between cores. In particular, when multiple cores access the same data concurrently, cache consistency management is required to ensure that the data remains up-to-date. Existing cache consistency protocols manage the state of cache lines and maintain consistency through processes of updating or invalidating data. However, these traditional methods complicate inter-core communication and control, and can lead to unnecessary data transmission or processing delays in certain situations. In particular, there is a need for improvements regarding methods to efficiently invalidate cache lines when they are maintained with outdated data. The information described above may be provided as related art for the purpose of aiding understanding of the present disclosure. No claim or determination is made as to whether any of the foregoing may be applied as prior art related to the present disclosure. Figure 1 is a diagram illustrating how the private cache of each core in the MESI protocol manages the state of the cache line. FIG. 2 is a diagram illustrating how the private cache of each core manages the state of the cache line in a protocol according to one embodiment. FIG. 3 is a flowchart for explaining the operation method of a multi-core processor according to one embodiment. Figure 4 is a diagram illustrating the structure and operation of the deadline buffer and the address buffer. Figure 5 is a flowchart illustrating how to remove timed-out cache lines from the cache and directory. FIG. 6 is a flowchart illustrating a method for accepting a new Load.T request according to one embodiment. FIG. 7 is a diagram illustrating a mechanism in which a timeout occurs when a specific bit of an RTC is set according to a condition in accordance with one embodiment. The specific structural or functional descriptions disclosed in this specification are illustrative of embodiments according to technical concepts only, and the actual implemented form may take various other forms and is not limited to the embodiments described in this specification. Terms such as "first" or "second" may be used to describe various components, but these terms should be understood solely for the purpose of distinguishing one component from another. For example, the first component may be named the second component, and similarly, the second component may be named the first component. When it is stated that one component is "connected" or "connected" to another component, it should be understood that while it may be directly connected or connected to that other component, there may also be other components in between. Conversely, when it is stated that one component is "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between. Expressions describing the relationships between components, such as "between" and "directly between," or "adjacent to" and "directly adjacent to," should be interpreted in the same way. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this specification, terms such as “comprising” or “having” are intended to specify the existence of the implemented features, numbers, steps, actions, components, parts, or combinations thereof, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof. Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this specification. The embodiments can be implemented in various forms of products, such as personal computers, laptop computers, tablet computers, smartphones, televisions, smart home appliances, intelligent vehicles, kiosks, and wearable devices. The embodiments will be described in detail below with reference to the attached drawings. Identical reference numerals in each drawing indicate identical components. Figure 1 is a diagram illustrating how the pr